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Patent # Description
US-1,026,1913 Persistent memory for key-value storage
Using persistent memory for key-value storage is disclosed, including: receiving a put key operation including a key and a corresponding value; directly storing...
US-1,026,1912 Apparatus and methods implementing dispatch mechanisms for offloading executable functions
An apparatus includes a first processor to execute a user-level application to operate in a virtual address, and a co-processor to execute a computing kernel...
US-1,026,1911 Apparatus and method for computational workflow management
Apparatuses and methods for performing computational workflow management are provided. An example apparatus may include processing circuitry. The processing...
US-1,026,1910 Cache line compaction of compressed data segments
Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying,...
US-1,026,1909 Speculative cache modification
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a speculative...
US-1,026,1908 Method and apparatus for expanding cache size for cache array
There is provided a method and apparatus of expanding capacity for a cache array. The method includes in response to detecting that a first new cache disk is to...
US-1,026,1907 Caching data in a redundant array of independent disks (RAID) storage system
Caching data in a redundant array of independent disks (RAID) storage system including receiving an operation instruction targeting a location in an attached...
US-1,026,1906 Data accessing method and apparatus
A data accessing method includes: determining whether a preset cache area has cached data that a read target address points to when receiving a read instruction...
US-1,026,1905 Accessing cache with access delay reduction mechanism
A method for accessing a cache including reading an access instruction for acquiring data; determining, according to a delay identifier carried by the access...
US-1,026,1904 Memory sequencing with coherent and non-coherent sub-systems
Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated...
US-1,026,1903 Extend GPU/CPU coherency to multi-GPU cores
In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit...
US-1,026,1902 Parallel processing of a series of data units for writing
A storage system includes a plurality of storage devices, and a server including a memory and an interface. The server is configured to store, in the memory,...
US-1,026,1901 Method and apparatus for unneeded block prediction in a computing system having a last level cache and a...
An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system...
US-1,026,1900 Data cache system, recording medium and method
A transmission device (300) comprising a data cache system is provided with a data acquisition part (315) for acquiring volume data indicating the volume of...
US-1,026,1899 Method, device and system for data processing using dedicated mapping between logical and physical addresses
A method for data processing including mapping between a logical address and a physical address of a memory, wherein the memory comprises several pages, wherein...
US-1,026,1898 Concurrent marking of location and shape changing objects
Aspects of the subject technology relate to concurrent marking of objects in memory. A garbage collection process accesses objects in a marking deque. The...
US-1,026,1897 Tail latency aware foreground garbage collection algorithm
A Solid State Drive (SSD) is disclosed. The SSD may include a host interface logic to receive a write command from a host and flash memory to store data. The...
US-1,026,1896 Self tuning adaptive bucket memory manager
Disclosed herein are system, method, and computer program product embodiments for adaptively self-tuning a bucket memory manager. An embodiment operates by...
US-1,026,1895 System and method for transferring execution of a computer program
Disclosed are system and method for controlling execution of a computer program. An example method includes determining, by a processor, a memory sector for...
US-1,026,1894 System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode
In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a...
US-1,026,1893 Implicit coordination of deployment and regression testing across data centers and system clusters
The disclosed methods and systems for coordinating deployment and regression testing across data centers and system clusters in multiple service clouds include...
US-1,026,1892 Cloud-based automated test execution factory
Method and apparatus for efficient test execution in a testing environment is provided. The method may include a test file. The test file may include one or...
US-1,026,1891 Automated test input generation for integration testing of microservice-based web applications
Techniques for automated generation of inputs for testing microservice-based applications are provided. In one example, a computer-implemented method comprises:...
US-1,026,1890 Methods and systems for executing tests using grouped/filtered test classes during testing of an application
Computer implemented methods and systems are provided for executing tests in a system that includes a user system and a cloud-based computing platform. The user...
US-1,026,1889 Techniques for edit-and-continue and enhanced optimized debugging on optimized code
Methods, systems, and computer program products are provided that enable a portion of code to be marked in source code to disable compilation optimizations for...
US-1,026,1888 Emulating an environment of a target database system
A test system receives environment information of a target database system, where the environment information includes information relating to hardware and...
US-1,026,1887 Method and system for computerized debugging assertions
A method for assertion debugging may include identifying in signals relating to an execution run of a code a segment of time for which an assertion has failed....
US-1,026,1886 Function call visualization
In one example in accordance with the present disclosure, a system may include a processor and a memory comprising instructions executable by the processor to...
US-1,026,1885 Debug event handling
Systems and methods are disclosed for debug event handling. For example, methods may include receiving a request from a client device. Methods may include,...
US-1,026,1884 Method for correcting violation of source code and computer readable recording medium having program performing...
The present disclosure relates to a method for correcting violation of a source code and a computer readable recording medium having a program performing the...
US-1,026,1883 Aggregating source code metric values
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for aggregating source code metric values. One of the methods...
US-1,026,1882 Functional unit promotion to management unit
A system comprises a plurality of functional units powered via a power source. The system further comprises a first functional unit and a second functional...
US-1,026,1881 Information processing apparatus, information processing system, information processing method, computer...
An information processing apparatus includes: an operating unit capable of recognizing a peripheral apparatus. The operating unit includes: a first recognizing...
US-1,026,1880 Error generation using a computer add-in card
A smart add-in card can be leveraged to perform testing on a host server computer. The add-in card can include an embedded processor and memory. Tests can be...
US-1,026,1879 Instruction and logic to test transactional execution status
Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start...
US-1,026,1878 Stress testing a processor memory with a link stack
A processor memory is stress tested with a variable link stack depth using link stack test segments with non-naturally aligned data boundaries. Link stack test...
US-1,026,1877 Systems and methods for testing mobile devices
Systems and methods for testing mobile device s are disclosed. In an embodiment, a mobile device testing system comprises a non-transitory memory and one or...
US-1,026,1876 Memory management
The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of...
US-1,026,1875 Runtime optimization of multi-core system designs for increased operating life and maximized performance
Aspects include computing devices, systems, and methods for managing a first computing device component of a computing device in order to extend an operating...
US-1,026,1874 Enabling a cloud controller to communicate with power systems
An approach is disclosed that receives power related data from one or more power systems. The approach then determines, based on an analysis of the power...
US-1,026,1873 Failure resistant distributed computing system
A failure resistant distributed computing system includes primary and secondary datacenters each comprising a plurality of computerized servers. A control...
US-1,026,1872 Multilevel disaster recovery
Account data comprising metadata for primary application instances running at a primary active cloud environment instance (ACEI) is stored. Application data...
US-1,026,1871 Modification of a cluster of communication controllers
Provided is a system having a cluster of communication controllers, a method for modification of the latter, and a computer program product carrying computer...
US-1,026,1870 Risk formula for erroneous software components detection
A method for performing software error detection and prediction. The method includes identifying a plurality of software components in a computer software...
US-1,026,1869 Transaction processing using torn write detection
Performing a transaction in the context of a computing system that has one or more persistent systems coupled to one or more processors over a bus. As an...
US-1,026,1868 Using a forward log storage and backward log storage to recover a storage to a forward or backward point-in-time
Provided are a computer program product, system, and method for using a forward log storage and backward log storage to recover a storage to a forward or...
US-1,026,1867 Intelligent point-in-time selector
A system and method for selecting point-in-time copies of data objects for restore operations. A user operates a mobile device with a touch screen, which is...
US-1,026,1866 Restoring data
Restoring a data processing system. Files on one or more storage devices of a data processing system are backed up to magnetic tape recording media. Metadata...
US-1,026,1865 Fast and optimized restore using delta information
An indication of one or more changes to file system data since a last backup snapshot is received. One or more changes to the file system data between a...
US-1,026,1864 System and method for dynamic transparent consistent application-replication of multi-process multi-threaded...
A system, method, and computer readable medium for consistent and transparent replication of multi process multi threaded applications. The computer readable...
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