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Patent # Description
US-1,027,6588 HKMG high voltage CMOS for embedded non-volatile memory
The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-.kappa. metal gate) integrated circuit which...
US-1,027,6587 NVM memory HKMG integration technology
The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a...
US-1,027,6586 Semiconductor device and method for manufacturing same
According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is...
US-1,027,6585 Semiconductor memory device
A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided...
US-1,027,6584 Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD)...
A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a...
US-1,027,6583 Three-dimensional memory device containing composite word lines including a metal silicide and an elemental...
Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material...
US-1,027,6582 High coupling ratio split gate memory cell
A split gate non-volatile memory (NVM) cell formed on a crystalline-on-insulator (COI) substrate, such as a fully or partially depleted silicon-on-insulator...
US-1,027,6581 Integrated circuit chip and manufacturing method thereof
An integrated circuit chip includes a substrate, a first type memory cell, and a second type memory cell. The first type memory cell is disposed over the...
US-1,027,6580 Methods, structures and devices for intra-connection structures
Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate...
US-1,027,6579 Layout design for manufacturing a memory cell
Arrays of static random access memory (SRAM) cells and methods of fabricating the same are provided. A first communication path is disposed a first distance...
US-1,027,6578 Dynamic oxide semiconductor random access memory(DOSRAM) having a capacitor electrically connected to the...
The present invention provides a semiconductor memory circuit, the semiconductor memory circuit includes a static random access memory (SRAM), having a first...
US-1,027,6577 Semiconductor memory device and manufacturing method thereof
A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping...
US-1,027,6576 Gated diode memory cells
Examples relate generally to the field of semiconductor memory devices. In an example, a memory cell may include an access device coupled to an access line and...
US-1,027,6575 Multi-threshold voltage field effect transistor and manufacturing method thereof
The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a...
US-1,027,6574 Semiconductor device and manufacturing method thereof
A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin,...
US-1,027,6573 FinFET including tunable fin height and tunable fin width ratio
A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to...
US-1,027,6572 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and...
US-1,027,6571 Circuit design system and semiconductor circuit designed by using the system
A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example...
US-1,027,6570 Semiconductor device
A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns;...
US-1,027,6569 Minimizing shorting between FinFET epitaxial regions
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in...
US-1,027,6568 Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the...
US-1,027,6567 Semiconductor device
Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate...
US-1,027,6566 Leakage current suppression methods and related structures
A method and structure for suppressing band-to-band tunneling current in a semiconductor device having a high-mobility channel material includes forming a...
US-1,027,6565 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate; a first device disposed on the substrate, and the first device includes at least two first gate stacks, in which...
US-1,027,6564 Semiconductor device including vertical channel
A semiconductor device includes a substrate having a first region and a second region; a first nanowire in the first region in a direction perpendicular to an...
US-1,027,6563 Semiconductor devices and methods for forming the same
A semiconductor device and a method for forming the same are provided. The method includes forming a patterned mask on a substrate, wherein the patterned mask...
US-1,027,6562 Semiconductor device with multiple threshold voltage and method of fabricating the same
According to an exemplary embodiment, a chip is provided. The chip includes a first vertical device having a first threshold and second vertical device having a...
US-1,027,6561 Semiconductor structure with resistor layer and method for forming the same
A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes transferring the substrate...
US-1,027,6560 Passive device structure and methods of making thereof
Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric...
US-1,027,6559 System and method of fabricating ESD FinFET with improved metal landing in the drain
A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the...
US-1,027,6558 Electrostatic discharge protection using vertical fin CMOS technology
Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment,...
US-1,027,6557 Electrostatic discharge protection device
An ESD protection device includes a semiconductor substrate of p-type conductivity, an epitaxial layer of p-type conductivity, a buried layer of n-type...
US-1,027,6556 Semiconductor device having biasing structure for self-isolating buried layer and method therefor
A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major...
US-1,027,6555 Method and system for providing a magnetic cell usable in spin transfer torque applications and including a...
A magnetic cell and method for providing the magnetic cell are described. A magnetic cell resides on a substrate and is usable in a magnetic device. The...
US-1,027,6554 Integrated standard cell structure
An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard...
US-1,027,6553 Chip package structure and manufacturing method thereof
A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is...
US-1,027,6552 Semiconductor module
A semiconductor module, comprises a substrate plate; a semiconductor switch chip and a diode chip attached to a collector conductor on the substrate plate,...
US-1,027,6551 Semiconductor device package and method of forming semiconductor device package
A semiconductor device package includes a redistribution structure, a first semiconductor device, a plurality of second semiconductor devices, at least one...
US-1,027,6550 Light emitting diode display and manufacture method thereof
The present invention provides a light emitting diode display and a manufacture method thereof. The manufacture method of the light emitting diode forms the...
US-1,027,6549 Package structure with dummy die
A package structure and method for forming the same are provided. The package structure includes a package component, and a device die formed over the package...
US-1,027,6548 Semiconductor packages having dummy connectors and methods of forming same
An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit...
US-1,027,6547 Image display module and method of manufacturing the same, and display device
The present disclosure provides an image display module and a method of manufacturing the same, and a display device. The image display module includes a...
US-1,027,6546 Semiconductor device with die tilt control
A semiconductor device with die tilt control is disclosed. In one embodiment, a semiconductor device is provided comprising: a substrate; a first semiconductor...
US-1,027,6545 Semiconductor package and manufacturing method thereof
A semiconductor package including a chip stack, at least one conductive wire, a first insulating encapsulant, a second insulating encapsulant, and a...
US-1,027,6544 Semiconductor package
A semiconductor package includes a board, a plurality of semiconductor memory chips, a controller chip, and a sealing resin portion. The plurality of...
US-1,027,6543 Semicondcutor device package and method of forming semicondcutor device package
A semiconductor device package includes a lower redistribution structure, an upper encapsulated semiconductor device and an upper redistribution structure. The...
US-1,027,6542 Package structure and manufacturing method thereof
A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through...
US-1,027,6541 3D package structure and methods of forming same
An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first...
US-1,027,6540 Chip packaging method and chip packaging structure
A packaging method and a packaging structure are provided. The method includes: providing a first substrate and a second substrate, the second substrate having...
US-1,027,6539 Method for 3D ink jet TCB interconnect control
A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a pillar. The...
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