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Patent # Description
US-1,027,6487 Semiconductor device with flexible circuit for enabling non-destructive attaching and detaching of device to...
A semiconductor device assembly that includes a flexible member having a first portion connected to a substrate and a connector attached to a second portion of...
US-1,027,6486 Stress resistant micro-via structure for flexible circuits
A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer...
US-1,027,6484 Package with metal-insulator-metal capacitor and method of manufacturing the same
A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A...
US-1,027,6483 Coaxial vias
Embodiments herein may relate to a substrate that includes a coaxial via with a signal portion and a ground shield portion. In embodiments, the via may further...
US-1,027,6482 Method for reinforcing conductor tracks of a circuit board
A method for manufacturing a circuit carrier for electronic components includes making available a carrier material layer made of an electrically insulating...
US-1,027,6481 Package structure having a plurality of conductive balls having narrow width for the ball waist
A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is...
US-1,027,6480 Semiconductor structure
A substrate structure includes a dielectric layer, a first circuit layer, a second circuit layer and at least one conductive pillar. The dielectric layer has a...
US-1,027,6479 Methods of processing semiconductor devices
Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing...
US-1,027,6478 Lead frame
A lead frame includes an outer frame. The outer frame includes: an upper surface; a lower surface that is opposite to the upper surface; a side surface between...
US-1,027,6477 Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing...
US-1,027,6476 Semiconductor device and method of forming the same
A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device includes a substrate, an interconnection...
US-1,027,6475 Thermal conductive stress relaxation structure
A thermal conductive stress relaxation structure is interposed between a high-temperature substance and a low-temperature substance to conduct heat in a...
US-1,027,6474 Semiconductor device
A semiconductor device includes a plurality of semiconductor elements; insulating circuit boards each including an insulating substrate, a circuit portion on a...
US-1,027,6473 Easily detachable CPU clip
A clip for use with an electronic package, includes a frame structure with a pair of first side bars and a pair of second side bars commonly defining a...
US-1,027,6472 Heat transfer plate having small cavities for taking up a thermal transfer material
A power semiconductor device module includes, among other parts, a DMB structure. The DMB structure includes a ceramic sheet, a top metal plate that is directly...
US-1,027,6471 Package and method for integration of heterogeneous integrated circuits
In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad...
US-1,027,6470 Semiconductor device having an electric field relaxation structure
Semiconductor device 1000 includes semiconductor 102, an electric field relaxation structure, at least one surface electrode 112, passivation layer 114, and...
US-1,027,6469 Method for forming semiconductor device structure
A method for forming a semiconductor device structure is provided. The method includes performing a first process over a surface of a semiconductor substrate....
US-1,027,6468 Circuit package
A circuit package comprises a circuit device in a first epoxy mold compound and a second epoxy mold compound of different compositions.
US-1,027,6467 Fan-out semiconductor package
A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor...
US-1,027,6466 Semiconductor device and semiconductor device mounting method
A semiconductor device of the present invention includes: a substrate (12) that is annular or partially annular, the substrate (12) having an inner...
US-1,027,6465 Semiconductor package assembly
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a core substrate formed of a first material having a...
US-1,027,6464 Semiconductor device
Provided is a technique of reducing detachment of a sealing resin in a semiconductor device, thereby achieving an increased improvement in lifetime of the...
US-1,027,6463 Semiconductor device and method for manufacturing the same
A semiconductor device includes a substrate with a recess subsiding from a selected surface of the substrate to accommodate a semiconductor element. Connected...
US-1,027,6462 Lid, and optical device package
A lid constitutes, together with a housing, a package that encloses an optical element. The lid includes a frame plate divided into a first member and a second...
US-1,027,6461 Split probe pad structure and method
A structure and method for forming a split probe pad structure for a semiconductor structure. The split probe pad structure may include a first probe pad...
US-1,027,6460 Endpointing detection for chemical mechanical polishing based on spectrometry
A method of detecting a polishing endpoint includes storing a plurality of library spectra, measuring a sequence of spectra from the substrate in-situ during...
US-1,027,6459 Measurement method, measurement program, and measurement system
According to one embodiment, there is provided a measurement method. The method includes acquiring layer information related to a plurality of layers to be...
US-1,027,6458 Method for testing bridging in adjacent semiconductor devices and test structure
Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first...
US-1,027,6457 Method for measuring charge accumulation in fabrication process of semiconductor device and method for...
A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a...
US-1,027,6456 Array substrate, its manufacturing method and testing method, and display device
The present disclosure provides an array substrate, its manufacturing method and testing method, and a display device. The array substrate includes a (Test...
US-1,027,6455 System and method for measurement of semiconductor device fabrication tool implement
Methods, and corresponding systems, are described that include providing a laser-based measurement tool. An implement of a semiconductor fabrication process...
US-1,027,6454 Semiconductor substrate having amorphous and single crystalline III-V compound semiconductor layers
A semiconductor device, a semiconductor substrate and a method of forming the same are disclosed. The semiconductor substrate includes a first ...
US-1,027,6453 Circuits constructed from stacked field-effect transistors
Structures that include vertically-arranged field-effect transistors and methods for forming a structure that includes vertically-arranged field-effect...
US-1,027,6452 Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
A method of forming a semiconductor structure includes forming first and second stacked nanosheet channel structures on a semiconductor substrate, with each...
US-1,027,6451 Semiconductor structure and method for forming the same
A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure...
US-1,027,6450 Fabrication technology for metal gate
One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer...
US-1,027,6449 Method for forming fin field effect transistor (FinFET) device structure
A method for forming a semiconductor device structure includes providing a substrate having a first fin structure and a second fin structure that are capped by...
US-1,027,6448 Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first...
US-1,027,6447 Semiconductor structures and methods of forming the same
A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion...
US-1,027,6446 Method of adjusting signal to noise ratio of SRAM and invertor structure
An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor...
US-1,027,6445 Leakage reduction methods and structures thereof
A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell...
US-1,027,6444 Method of forming oxide layer for FinFET device
A method for forming a fin-based transistor includes forming a fin on a substrate; overlaying at least an upper portion of the fin with nitrogen-based radicals,...
US-1,027,6443 Insulating layer next to fin structure and method of removing fin structure
A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of...
US-1,027,6442 Wrap-around contacts formed with multiple silicide layers
Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A first field-effect transistor has a first...
US-1,027,6441 Protected chip-scale package (CSP) pad structure
A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a...
US-1,027,6440 Removable temporary protective layers for use in semiconductor manufacturing
A method for temporarily protecting a semiconductor device wafer during processing includes preparing a solution including poly(vinyl alcohol) and water,...
US-1,027,6439 Rapid oxide etch for manufacturing through dielectric via structures
After bonding a second substrate to a first substrate through a bonded material layer to provide a bonded structure, through dielectric via (TDV) openings of...
US-1,027,6438 Marked pixel unit, display device using the same, and method for fabricating the display device
A marked pixel unit includes at least one active element, a first dielectric layer, a color filter unit, a second dielectric layer, and at least one pixel...
US-1,027,6437 Contact structure of gate structure
A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first...
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