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Patent # Description
US-1,027,6436 Selective recessing to form a fully aligned via
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and...
US-1,027,6435 Advanced copper interconnects with hybrid microstructure
A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the...
US-1,027,6434 Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration
Semiconductor devices and methods to fabricate the devices are provided. For example, a semiconductor device includes a back-end-of-line (BEOL) structure formed...
US-1,027,6433 Method for fabricating planarization layer
A method for fabricating a planarization layer includes: forming an active device on a substrate; covering the active device with a passivation layer; forming a...
US-1,027,6432 Composite contact plug structure and method of making same
An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer...
US-1,027,6431 Device and method for reducing contact resistance of a metal
A device comprises a semiconductor substrate; a dielectric layer deposited over the semiconductor substrate, the dielectric layer including a trench; and a...
US-1,027,6430 Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method
Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer (54) covering a metal...
US-1,027,6429 Interconnect structure, interconnect layout structure, and manufacturing method thereof
An interconnect layout structure having air gaps includes a plurality of air gaps extended along a direction, and at least a first interconnect unit disposed in...
US-1,027,6428 Semiconductor package and method of fabricating semiconductor package
A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate....
US-1,027,6427 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench...
US-1,027,6426 System and method for performing spin dry etching
A spin dry etching process includes loading an object into a dry etching system. A dry etching process is performed to the object, and the object is spun while...
US-1,027,6425 Substrate processing system
A substrate processing system includes: a holding plate provided to be rotatable around a vertical axis; a substrate holding member provided on the holding...
US-1,027,6424 Method and apparatus for wafer level packaging
Methods and apparatus for wafer level packaging are described herein. According to one embodiment, a method comprises depositing an adhesive layer atop a...
US-1,027,6423 Method of manufacturing element chip
A method of manufacturing a semiconductor chip includes: preparing a semiconductor wafer; forming a mask on a front surface of the semiconductor wafer so as to...
US-1,027,6422 Semiconductor device substrate, semiconductor device wiring member and method for manufacturing them, and...
A semiconductor device substrate and wiring member including a first noble metal plating layer to become internal terminals is formed at predetermined sites on...
US-1,027,6421 Integrated fan-out package, integrated fan-out package array, and method of manufacturing integrated fan-out...
An integrated fan-out package including a die, an insulating encapsulation, a filler, and a redistribution circuit structure is provided. The insulating...
US-1,027,6420 Electrostatic chuck and semiconductor manufacturing apparatus
An electrostatic chuck includes a first electrode provided in a first plane, a second electrode provided in a second plane parallel to the first plane, and an...
US-1,027,6419 Pick and place device with interdigitated electrodes for micro scale device
A compliant electrostatic transfer head and array are described. In an embodiment a compliant electrostatic transfer head includes a base substrate, and a...
US-1,027,6418 Silicon wafer pre-alignment device and method therefor
A wafer pre-alignment device is disclosed, including a first unit configured to drive a wafer to rotate or move upward or downward, a second unit configured to...
US-1,027,6417 Pre-alignment device and method for wafer
An apparatus for pre-aligning a wafer comprises: a wafer stage for carrying the wafer, wherein a first alignment mark (W1) and a second alignment mark (W2) are...
US-1,027,6416 Industrial robot
An industrial robot may include a first hand and a second hand, each of which is provided with a first hand portion including a substrate-mounting portion and a...
US-1,027,6415 Gas purge unit
A gas purge unit introduces a cleaning gas into a container with a main opening there through for taking a housed object in and out. The gas purge unit includes...
US-1,027,6414 Thin wafer shipper
An improved wafer support mechanism in a wafer container useful for carrying a plurality of axially aligned thin mostly circular wafer substrates. The container...
US-1,027,6413 Laser processing apparatus
A laser processing apparatus includes a melt processing unit for processing a melt formed by laser processing, the melt processing unit being disposed...
US-1,027,6412 Heating arrangement and method for heating substrates
The invention relates to a vacuum processing system for processing a substrate (2), with an enclosure (1) for carrying the substrate (2) to be treated in a...
US-1,027,6411 High pressure and high temperature anneal chamber
Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is...
US-1,027,6410 Substrate support device
A substrate support device formed of a metal and having a high withstand voltage and a high thermal resistance is provided. A substrate support device according...
US-1,027,6409 Sample holder, device and method for detaching of a first substrate
A method and device for detaching a first substrate, which is connected to a second substrate by an interconnect layer, from the second substrate by...
US-1,027,6408 Flow-rate regulator device, diluted chemical-liquid supply device, liquid processing apparatus and its...
A flow-rate regulator device for controlling a flow rate of a liquid includes a first flow-rate regulator component positioned on an upstream side of a liquid...
US-1,027,6407 Substrate processing apparatus and substrate processing method
The substrate processing apparatus includes a substrate holding unit that holds a substrate horizontally, a substrate rotating unit that rotates the substrate...
US-1,027,6406 Substrate processing device and substrate processing method
A substrate processing device includes a suction drying section drying a surface of a substrate by absorbing and removing a liquid droplet of volatile solvent...
US-1,027,6405 Plasma processing apparatus
A plasma processing apparatus includes: a processing container; a processing gas supply unit; a mounting table configured to mount a to-be-processed substrate...
US-1,027,6404 Integrated fan-out package
An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The die is...
US-1,027,6403 High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer
An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated...
US-1,027,6402 Semiconductor package and manufacturing process thereof
A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated...
US-1,027,6401 3D shielding case and methods for forming the same
A package includes a die, and a molding material molding the die therein. A metal shield case includes a first metal mesh over and contacting the molding...
US-1,027,6400 Method for fabricating array substrate, array substrate and display device
The invention relates to a method for fabricating an array substrate, an array substrate and a display device. The method for fabricating an array substrate may...
US-1,027,6399 FinFET doping methods and structures thereof
A method and structure for providing conformal doping of FinFET fin structures, for example by way of a thermal treatment process, includes forming a gate stack...
US-1,027,6398 High aspect ratio selective lateral etch using cyclic passivation and etching
Methods and apparatus for laterally etching unwanted material from the sidewalls of a recessed feature are described herein. In various embodiments, the method...
US-1,027,6397 CVD metal seed layer
The present disclosure relates to an improved method of forming interconnection layers to reduce voids and improve reliability, and an associated device. In...
US-1,027,6396 Method for forming semiconductor device with damascene structure
A method for forming a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate and forming an etch stop layer...
US-1,027,6395 Method for manufacturing semiconductor device
The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the...
US-1,027,6394 Hybrid double patterning method for semiconductor manufacture
A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC...
US-1,027,6393 Method of manufacturing semiconductor device
In a method of manufacturing a semiconductor device, by performing a predetermined number of times a cycle of performing supplying reducing gas to a substrate...
US-1,027,6392 Loading effect reduction through multiple coat-etch processes
First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first,...
US-1,027,6391 Self-aligned gate caps with an inverted profile
Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate structure includes a work function metal layer,...
US-1,027,6390 Method and apparatus for reducing threshold voltage mismatch in an integrated circuit
A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the...
US-1,027,6389 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the...
US-1,027,6388 Laser machining device and laser machining method
A laser processing apparatus 1 is an apparatus for forming a modified region R in an object to be processed S by irradiating the object S with laser light L....
US-1,027,6387 Semiconductor device including superjunction structure formed using angled implant process
A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N...
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