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Patent # Description
US-1,028,4247 System and method for bit processing in a central network component
A central network component, a FlexRay-compatible central network component, and a method for bit processing in a central network component are described. In...
US-1,028,4246 Card holder and electronic device
Disclosed are a card holder and an electronic device. The electronic device includes: a device body provided with a card holder slot and a card holder installed...
US-1,028,4245 Enhanced modem based carrier auto-selection algorithm
Aspects of the present disclosure includes a method of performing enhanced auto-selection in a UE including initiating the UE having at least a first subscriber...
US-1,028,4244 Method and apparatus for coupling one or more transceivers to a plurality of antennas
The present application provides a radio frequency front end circuit, a wireless communication device and a method for coupling signals in support of multiple...
US-1,028,4243 Apparatus and method for tuning frequency
A frequency tuning apparatus includes: a frequency tuner configured to tune an oscillation frequency of an oscillator based on target information extracted from...
US-1,028,4242 Custom broadcast audio content station
A system may be configured to scan audio content providers, using at least one receiver, to identify metadata of audio content instances currently being...
US-1,028,4241 Receivers and methods for reducing an interference component in a receive signal
A receiver for reducing an interference component in a receive signal is provided. The interference component is caused by a first interferer emitting payload...
US-1,028,4240 Receiving circuit and wireless communication device
A receiving circuit includes a first inductor, a second inductor, a capacitor and an amplifier. The first inductor includes a first terminal and a second...
US-1,028,4239 Antenna device
Disclosed is an antenna device including element antennas for receiving signals, phase control units for controlling the phases of the signals received by the...
US-1,028,4238 DC coupled radio frequency modulator
A radio frequency transmitter includes a digital-to-analog converter (DAC), a load circuit, and a modulator circuit. The load circuit is coupled to an output of...
US-1,028,4237 Systems and methods for a predistortion linearizer with frequency compensation
An analog predistortion linearizer system with dynamic frequency compensation for automatically adjusting predistortion characteristics based on a detected...
US-1,028,4235 Wireless transceiver with switch to reduce harmonic leakage
Disclosed herein are wireless transceivers with switches to reduce harmonic leakage. In some embodiments, a transmitter system includes a power amplification...
US-1,028,4234 Facilitation of data deletion for distributed erasure coding
Although a distributed storage device can recover data from multiple failures this process produces excessive inter-zone network traffic when a chunk with user...
US-1,028,4233 ECC adjustment based on dynamic error information
A device includes a memory, an error correction code (ECC) decoder, and an ECC input adjuster. The ECC decoder is configured to perform a first decode operation...
US-1,028,4232 Dynamic error processing in a storage device
Dynamically adjusting an error correction effort level of a storage device, including: receiving, from a storage array controller, an error correction effort...
US-1,028,4231 Adaptive outer code for consistent overprovisioning (OP) level
Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a solid-state non-volatile memory (NVM) has a...
US-1,028,4230 Linked storage system and host system error correcting code
Systems, methods, and software are provided herein for error correction in writing and reading data to and from a data storage device. In one implementation, an...
US-1,028,4229 Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
US-1,028,4228 Apparatus for time interleaving and method using the same
An apparatus and method for time interleaving corresponding to hybrid time interleaving mode are disclosed. An apparatus for time interleaving according to an...
US-1,028,4227 Parity puncturing device for fixed-length signaling information encoding, and parity puncturing method using same
A parity puncturing apparatus and method for fixed length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the...
US-1,028,4226 Performing parallel deflate compression
A computing system includes a network interface, a processor, and a decompression circuit. In response to a compression request from the processor the...
US-1,028,4225 Systems and methods for data compression
The transmission of broadcast data, such as financial data and news feeds, is accelerated over a communication channel using data compression and decompression...
US-1,028,4224 System and method for compressed sensing
A system for compressed sensing comprising: a compressive sampling module configured for providing a CS-sampled signal and a signal reconstruction module...
US-1,028,4223 Method of performing analog-to-digital conversion
The invention describes a method of performing analog-to-digital conversion on an input signal (P.sub.in) within a range (R1) using a sigma-delta modulator (1)...
US-1,028,4222 Delta-sigma converter with pre-charging based on quantizer output code
An analog-to-digital converter (ADC) device includes a delta-sigma modulator having at least one integrator and a quantizer configured to receive an output of...
US-1,028,4221 Power-efficient flash quantizer for delta sigma converter
A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner....
US-1,028,4220 Equalization circuit, a method of operating an equalization circuit and a system comprising an equalization...
The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable...
US-1,028,4219 Inbuilt threshold comparator
A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first...
US-1,028,4218 Voltage window
An example apparatus includes a windowing component. The windowing component may set a first voltage level as an upper bound for a voltage window and set a...
US-1,028,4217 Multi-path analog front end and analog-to-digital converter for a signal processing system
In accordance with embodiments of the present disclosure, a processing system may include multiple selectable processing paths for processing an analog signal...
US-1,028,4216 Calibration circuit and calibration method for successive approximation register analog-to-digital converter
A calibration circuit and calibration method for a successive approximation register analog-to-digital converter (SAR ADC) are disclosed. The SAR ADC includes a...
US-1,028,4215 Dynamic power switching in current-steering DACS
Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply...
US-1,028,4214 Filter circuit for filtering an input signal of an analogue-to-digital converter
The invention relates to a filter circuit (200) comprising at least a first filter line (210). The first filter line (210) has a first input circuit (10), a...
US-1,028,4213 Analog-to-digital converter reusing comparator for residue amplifier for noise shaping
Some or all of a comparator circuit of an analog-to-digital converter (ADC) circuit can be efficiently repurposed or reused for residue amplification for...
US-1,028,4211 Injection-locked oscillator and semiconductor device including the same
An injection-locked oscillator includes an oscillator and an injection circuit. The oscillator includes a first oscillation node through which a first...
US-1,028,4210 Open-loop voltage regulation and drift compensation for digitally controlled oscillator (DCO)
Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). In...
US-1,028,4209 Phase locked loop
A phase locked loop for generating a frequency chirp is disclosed. The phase locked loop comprises a phase frequency detector configured to receive a reference...
US-1,028,4208 Frequency tuning and/or frequency tracking of a mechanical system with low sensitivity to electrical feedthrough
An apparatus and method for frequency tuning/tracking between an electrical subsystem and a mechanical transducer subsystem is presented. An electromechanical...
US-1,028,4207 Method and apparatus for controlling mismatch in a voltage controlled oscillator array
Methods and systems are provided for adaptively configuring voltage-controlled oscillator (VCO) arrays, such as to reduce mismatches among the VCOs. A plurality...
US-1,028,4206 Oscillator, electronic device, and moving object
An oscillator includes: an oscillation stage circuit that is connected between a first electrode and a second electrode of a resonator and performs an...
US-1,028,4205 Adaptive bandwidth systems and methods
A clock generator and a method to control an associated system are described. The clock generator (e.g., a PLL) can include a charge pump that can generate a...
US-1,028,4204 Logic unit circuit and pixel driving circuit
There are provided a logic unit circuit and a pixel driving circuit, which relate to a display technical field and are used to solve the problem that technical...
US-1,028,4203 Pure memristive logic gate
According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure...
US-1,028,4202 Generating analog output from a field programmable gate array by combining scaled digital outputs
A system for generating analog output from a field programmable gate array. The field programmable gate array has a plurality of digital transceivers, each...
US-1,028,4201 High range positive voltage level shifter using low voltage devices
A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input...
US-1,028,4200 Linearity in radio-frequency devices using body impedance control
A process for fabricating a semiconductor die involves providing a semiconductor substrate, forming a first field-effect transistor on the semiconductor...
US-1,028,4199 Voltage tolerant termination presence detection
Apparatuses and methods associated with voltage tolerant termination presence detection for universal serial bus type-C connectors are disclosed herein. In...
US-1,028,4198 Memory systems with ZQ global management and methods of operating same
A memory system includes a memory module and a memory controller. The memory module includes a plurality of memory devices with corresponding ZQ calibration...
US-1,028,4197 Key
A key is provided, including: a magnetic component arranged to generate a magnetic field; a closed loop, herein the closed loop includes a preset device in...
US-1,028,4196 Multi-state capacitive button
In certain embodiments, a method includes applying voltage to a sensor that includes first and second electrode tracks, the sensor proximate to a conductor...
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