Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-1,028,3536 Array substrate, method for manufacturing the same, display device and mask plate
A method for manufacturing an array substrate includes (S1) forming a pattern including a gate electrode and a gate line, (S2) forming an insulating layer, (S3)...
US-1,028,3535 Display device and method for manufacturing the same
A method for producing a display device includes locating a substrate, including a plurality of pixels, on a jig including a magnet; locating a plate formed of...
US-1,028,3533 Transistor array panel including transistor with top electrode being electrically connected to source electrode...
A transistor array panel includes a transistor disposed on a substrate. The transistor includes a gate electrode, a source electrode, a drain electrode, a...
US-1,028,3532 Semiconductor device and display device including the semiconductor device
Provided is a novel semiconductor device. The semiconductor device comprises a first transistor and a second transistor. The first transistor comprises a first...
US-1,028,3531 Thin film transistor, method for manufacturing the same, and display device including the same
Disclosed is a thin film transistor including both an N-type semiconductor layer and a P-type semiconductor layer, a method for manufacturing the same, and a...
US-1,028,3530 Semiconductor device and method for manufacturing the same
A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate...
US-1,028,3529 Method of manufacturing thin-film transistor, thin-film transistor substrate, and flat panel display apparatus
A method of manufacturing a thin-film transistor includes forming an oxide semiconductor on a substrate, stacking an insulating layer and a metal layer on the...
US-1,028,3528 Thin film transistor array panel, liquid crystal display including the same, and manufacturing method thereof
A thin film transistor array panel, including: a first insulating substrate; a gate line disposed on the first insulating substrate and including a gate...
US-1,028,3527 Method of manufacturing semiconductor device
An SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating...
US-1,028,3526 Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding...
Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one...
US-1,028,3525 Non-volatile memory device having at least one metal and one semiconductor body extending through an electrode...
According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor...
US-1,028,3524 Methods of filling horizontally-extending openings of integrated assemblies
Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first...
US-1,028,3523 Semiconductor memory device with first and second semicondutor films in first and second columnar bodies
A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first...
US-1,028,3522 Three dimensional semiconductor memory device in which a channel layer has a stacked structure including an...
According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a...
US-1,028,3521 Semiconductor device having vertical cell strings and a vertical common source line
Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes source select lines, word lines, drain select lines,...
US-1,028,3520 Elevationally-extending string of memory cells individually comprising a programmable charge storage transistor...
An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise...
US-1,028,3519 Three dimensional NAND string memory device
A memory device including a substrate, at least one first stacked structure and at least one second stacked structure disposed on the substrate is provided. The...
US-1,028,3518 Semiconductor device and method of manufacturing the same
A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first...
US-1,028,3517 Semiconductor memory device and method of manufacturing the same
According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation...
US-1,028,3516 Stacked nanosheet field effect transistor floating-gate EEPROM cell and array
Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first...
US-1,028,3515 Semiconductor memory device
A semiconductor memory device includes a plurality of electrode layers stacked in a first direction; a semiconductor layer of a columnar shape extending through...
US-1,028,3514 Semiconductor device and method of manufacturing the same
The semiconductor device includes a stack, a plurality of channel structures passing through the stack, a coupling structure which is disposed below the stack...
US-1,028,3513 Three-dimensional memory device with annular blocking dielectrics and method of making thereof
A memory opening is formed through an alternating stack of insulating layers and sacrificial material layers located over a substrate. Annular recesses are...
US-1,028,3512 Semiconductor device and manufacturing method thereof
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate...
US-1,028,3511 Non-volatile memory
A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and...
US-1,028,3510 Semiconductor structure and method for forming the same
A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The...
US-1,028,3509 Semiconductor device and method for fabricating the same
A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri...
US-1,028,3508 Semiconductor device and fabricating the same
The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having...
US-1,028,3507 Semiconductor device and method for fabricating the same
A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped...
US-1,028,3506 Super-saturation current field effect transistor and trans-impedance MOS device
The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound...
US-1,028,3505 Dummy gate used as interconnection and method of making the same
Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor...
US-1,028,3504 Vertical FET with reduced parasitic capacitance
A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a...
US-1,028,3503 Metal gate structure and methods thereof
Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of...
US-1,028,3502 Semiconductor device
A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a...
US-1,028,3501 GaN-on-Si semiconductor device structures for high current/ high voltage lateral GaN transistors and methods of...
A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN...
US-1,028,3500 Methods of fabricating integrated circuits and devices with interleaved transistor elements
A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in...
US-1,028,3499 Heterojunction diode having an increased non-repetitive surge current
A heterojunction diode is provided, including first and second semiconductor layers made of III-N material, the layers being superposed to form a...
US-1,028,3498 LED chip having ESD protection
Disclosed herein is a light emitting diode chip having ESD protection. An exemplary embodiment provides a flip-chip type light emitting diode chip, which...
US-1,028,3497 Light-emitting diode chip
The present invention provides a light-emitting diode (LED) chip. The LED chip includes a LED structure and an electrostatic discharge (ESD) protection...
US-1,028,3496 Integrated circuit filler and method thereof
Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a...
US-1,028,3495 Mask optimization for multi-layer contacts
A semiconductor device includes two elongated active regions that include source/drain regions for multiple transistor devices, a first contact layer that...
US-1,028,3494 Microelectronics package with self-aligned stacked-die assembly
The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed...
US-1,028,3493 Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof
A first die includes a three-dimensional memory device and first copper pads. A second die includes a peripheral logic circuitry containing CMOS devices located...
US-1,028,3492 Laminated interposers and packages with embedded trace interconnects
Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical...
US-1,028,3491 Light emitting device package
A light emitting device package is provided. The light emitting device package may include a main body having a cavity including side surfaces and a bottom, and...
US-1,028,3490 Communicating optical signals between stacked dies
A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die....
US-1,028,3489 Light emitting device
A light emitting device, includes: three light emitting elements with different emission colors; and a package including a plurality of lead frames to...
US-1,028,3488 Semiconductor module
A semiconductor module includes: a substrate having an insulating layer and a connecting portion connecting front and rear surfaces of the insulating layer; a...
US-1,028,3487 Methods of forming integrated circuit package with thermally conductive pillar
Embodiments of the present disclosure relate to an integrated circuit (IC) package, including a molding compound positioned on a first die and laterally...
US-1,028,3486 Semiconductor package including package substrate and chip stack in which a lower chip has a respective dummy...
A semiconductor package includes a package substrate, semiconductor chips stacked on the package substrate, and electrical connectors that connect internal...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.