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Patent # Description
US-1,028,3485 Semiconductor device including conductive bump interconnections
A semiconductor device is disclosed including semiconductor die stacked in a stepped, offset configuration, where die bond pads of semiconductor die on...
US-1,028,3484 Low cost substrates
A mask is formed over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive layer. An electrolytic process is...
US-1,028,3483 Packaging method and package structure for image sensing chip
A packaging method and package structure for an image sensing chip are provided. The method includes: providing a wafer including a first surface and a second...
US-1,028,3482 Wire bonding methods and systems incorporating metal nanoparticles
Wire bonding operations can be facilitated through the use of metal nanoparticle compositions. Both ball bonding and wedge bonding processes can be enhanced in...
US-1,028,3481 Device packaging facility and method, and device processing apparatus utilizing DEHT
Provided are a device packing facility and method using DEHT and a device processing apparatus utilizing the DEHT. The device packaging facility includes a...
US-1,028,3480 Substrate structure with selective surface finishes for flip chip assembly
The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The...
US-1,028,3479 Package structures and methods of forming the same
Package structures and methods of forming the same are disclosed. A package structure includes at least one first integrated circuit, at least one second...
US-1,028,3478 Pressure contact type semiconductor device stack
To provide a pressure contact type semiconductor device stack which can uniformly pressurize pressure contact type semiconductor devices irrespective of...
US-1,028,3477 Method of fabricating 3-dimensional fan-out structure
A method of fabricating a 3D fan-out structure for an integrated circuit device includes providing a substrate carrier having first and second opposing surfaces...
US-1,028,3476 Adhesive bonding composition and electronic components prepared from the same
A curable resin or adhesive composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to...
US-1,028,3475 Power module assembly with dual substrates and reduced inductance
A power module assembly has a first substrate including a first layer, second layer and a third layer. The first layer is configured to carry a switch current...
US-1,028,3474 Chip package structure and method for forming the same
A method for forming a chip package structure is provided. The method includes forming a first dielectric layer over a carrier substrate. The first dielectric...
US-1,028,3473 Package structure and manufacturing method thereof
A package structure includes an insulating encapsulation, at least one first chip, a redistribution layer and a bonding layer. The at least one first chip is...
US-1,028,3472 Electrode for a semiconductor device of a ball grid array (BGA) type
A semiconductor device of the ball grid array (BGA) type, the device having an electrode, and a process of forming the electrode are disclosed. The electrode...
US-1,028,3471 Micro-connection structure and manufacturing method thereof
A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad...
US-1,028,3469 Method of forming a passivation layer
A method of forming a passivation layer on an integrated circuit (IC) chip including a device layer on a substrate. The method may include forming a crosslinked...
US-1,028,3468 Package structures
A package structure includes at least one semiconductor chip, an insulating encapsulation, and a redistribution circuit structure. The semiconductor chip has an...
US-1,028,3467 Semiconductor package
A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a...
US-1,028,3466 Polymer resin and compression mold chip scale package
A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to...
US-1,028,3465 Three terminal solid state plasma monolithic microwave integrated circuit
A solid state plasma monolithic microwave integrated circuit having single or multiple elemental devices with at least three terminals operating within the...
US-1,028,3464 Electronic device and manufacturing method of electronic device
An electronic device includes a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, a...
US-1,028,3463 Terahertz detector comprised of P-N junction diode
A method of forming a semiconductor detector including: forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the...
US-1,028,3462 Semiconductor devices with post-probe configurability
A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first...
US-1,028,3461 Info structure and method forming same
A method includes encapsulating a package component in an encapsulating material, with the encapsulating material including a portion directly over the package...
US-1,028,3460 Semiconductor device, manufacturing method thereof, and electric power conversion device
A technology is proposed in which the improvement of the capability of a semiconductor device can be realized by satisfying both reduction of leakage currents...
US-1,028,3459 Vanishing via for hardware IP protection from reverse engineering
A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an...
US-1,028,3458 Semiconductor device and method of manufacturing the same
A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on...
US-1,028,3457 Method for lithographically forming wafer identification marks and alignment marks
The present disclosure relates a method of forming substrate identification marks. In some embodiments, the method may be performed by forming a photosensitive...
US-1,028,3456 Lithography engraving machine for forming water identification marks and aligment marks
In some embodiments, the present disclosure relates a lithographic substrate marking tool. The lithographic substrate marking tool has a first lithographic...
US-1,028,3455 Manufacturing method of package structure having embedded bonding film
A manufacturing method of a package structure having an embedded bonding film comprises the following steps: forming a bonding film, forming a redistribution...
US-1,028,3454 Power semiconductor module
The present invention relates to a power semiconductor module, comprising at least two power semiconductor devices, wherein the at least two power semiconductor...
US-1,028,3453 Interconnect routing configurations and associated techniques
Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus...
US-1,028,3452 Three-dimensional memory devices having a plurality of NAND strings
Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a...
US-1,028,3451 Semiconductor device and method of manufacturing a semiconductor device
A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width...
US-1,028,3450 Method for forming semiconductor device structure having conductive structure with twin boundaries
A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes...
US-1,028,3449 Low stress vias
A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front...
US-1,028,3448 Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same
A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first...
US-1,028,3447 Power semiconductor module with partially coated power terminals and method of manufacturing thereof
A power semiconductor module includes one or more power semiconductor dies attached to a first main face of a substrate, a plastic housing attached to the...
US-1,028,3446 Wiring board including multiple wiring layers
A wiring board includes a base board and a plurality of wiring layers formed of a resin insulating film on the base board, wherein at least one of the wiring...
US-1,028,3445 Bonding of laminates with electrical interconnects
A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of...
US-1,028,3444 Semiconductor device and method of manufacturing the same
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a...
US-1,028,3443 Chip package having integrated capacitor
A semiconductor device includes a plurality of redistribution layers, a dielectric layer, and a conductive structure. The redistribution layers are formed...
US-1,028,3442 Interposer substrate and method of fabricating the same
An interposer substrate includes a first insulating layer having opposite first and second surfaces; a first wiring layer formed in the first insulating layer,...
US-1,028,3441 Method of integrating capacitors on lead frame in semiconductor devices
In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame...
US-1,028,3440 Semiconductor device and manufacturing method of semiconductor device
A semiconductor device includes: a frame; a first-external-terminal provided to a first side portion of the frame; a first substrate enclosed in the frame and...
US-1,028,3439 Fan-out semiconductor package including electromagnetic interference shielding layer
A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection...
US-1,028,3438 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate,...
A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a...
US-1,028,3437 Metal density distribution for double pattern lithography
Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall...
US-1,028,3436 Power electronics module with first and second coolers
A power electronics module comprises a first liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the first liquid cooler...
US-1,028,3435 Heat dissipation component and terminal device including heat dissipation component
A heat dissipation component includes a plate that presses a heat receiving portion against a heat generating portion, and a heat pipe installed at a first...
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