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Patent # Description
US-1,028,2314 Synchronization of computer peripheral effects
Synchronization of effects across multiple devices using local, distributed control, and eliminating the need for central direction of the effects with the...
US-1,028,2313 Universal serial bus smart hub
A USB smart hub may provide enhanced battery charging, data storage security, vendor matching, device authentication, data capture/debug, and role switching....
US-1,028,2312 Integrated circuit, method for protecting an integrated circuit and computer program product
According to a first aspect of the present disclosure, an integrated circuit is provided which comprises an active shield in a first layer and at least one...
US-1,028,2311 Configuring functional capabilities of a computer system
Provided is a method for configuring the functional capabilities of a computer system. The computer system may include a persistent memory and a replaceable...
US-1,028,2310 Arithmetic processing device and control method thereof
An arithmetic processing device includes a core, and a first control circuit that controls a memory request issued by the processing core. The first control...
US-1,028,2309 Per-page control of physical address space distribution among memory modules
Systems, apparatuses, and methods for implementing per-page control of physical address space distribution among memory modules are disclosed. A computing...
US-1,028,2308 Method and apparatus for reducing TLB shootdown overheads in accelerator-based systems
A method and apparatus for reducing TLB shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus...
US-1,028,2307 Lock-free shared hash map
Shared hash map implementations provide a linearizable programmatic interface to calling threads and support lock-free hash map operations. In addition to...
US-1,028,2306 Supporting secure memory intent
A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor...
US-1,028,2305 Selective purging of entries of structures associated with address translation in a virtualized environment
Selective purging of entries of structures associated with address translation. A request to purge entries of a structure associated with address translation is...
US-1,028,2304 Caching using an admission control cache layer
Exemplary methods, apparatuses, and systems receive from a client a request to access data from a client. Whether metadata for the data is stored in a first...
US-1,028,2303 Using cache lists for processors to determine tracks to demote from a cache
Provided are a computer program product, system, and method for using cache lists for processors to determine tracks in a storage to demote from a cache. Tracks...
US-1,028,2302 Programmable memory-side cache management for different applications
Examples disclosed herein relate to programmable memory-side cache management. Some examples disclosed herein may include a programmable memory-side cache and a...
US-1,028,2301 Method and system for hardware accelerated read-ahead caching
A system and method for efficient cache buffering are provided. The disclosed method determining that a read-ahead operation is to be performed in response to...
US-1,028,2300 Accessing physical memory from a CPU or processing element in a high performance manner
A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor...
US-1,028,2299 Managing cache partitions based on cache usage information
Partition information includes entries that each include an entity identifier and associated cache configuration information. A controller manages memory...
US-1,028,2298 Store buffer supporting direct stores to a coherence point
A system that uses a write-invalidate protocol has two types of stores: a traditional store that operates using a write-back policy that snoops for copies of...
US-1,028,2297 Read-with overridable-invalidate transaction
A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a ...
US-1,028,2296 Zeroing a cache line
Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and...
US-1,028,2295 Reducing cache footprint in cache coherence directory
A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of...
US-1,028,2294 Mitigating DRAM cache metadata access overhead with SRAM metadata cache and bloom filter
A system and method for mitigating overhead for accessing metadata for a cache in a hybrid memory module are disclosed. The method includes: providing a hybrid...
US-1,028,2293 Method, switch, and multiprocessor system using computations and local memory operations
A memory access method includes: receiving, by the switch, a data packet; matching a flow table on the data packet, where the flow table includes at least one...
US-1,028,2292 Cluster-based migration in a multi-level memory hierarchy
Cluster manager functional blocks perform operations for migrating pages in portions in corresponding migration clusters. During operation, each cluster manager...
US-1,028,2291 Storage system with data management mechanism and method of operation thereof
A method of operation of a storage system includes: accessing a storage tier manager coupled to a first tier storage and a second tier storage; identifying a...
US-1,028,2290 Analyzing device management system
An information management system for detecting not only a set of management target data which has been changed but also another set of management target data...
US-1,028,2289 Package modules and methods of testing operations of chips included therein
A package module may be provided. The package module may include a first chip and a second chip. The first chip may be configured to receive first pattern data...
US-1,028,2288 Memory system and method for controlling nonvolatile memory
According to one embodiment, a memory system includes a nonvolatile memory, and a controller electrically connected to the nonvolatile memory. The controller...
US-1,028,2287 Interleaved direct access mode in byte addressible memory and related devices and systems
Memory devices and systems having direct access mode (DAM) space allocation across interleaved non-volatile memory (NVM) modules, as well as methods of...
US-1,028,2286 Address mapping using a data unit type that is variable
The present disclosure includes methods, memory units, and apparatuses for address mapping. One method includes providing a mapping unit having logical to...
US-1,028,2285 Human interface module for motor drive
A power electronics device with an improved human interface module (HIM) is provided. More specifically, a motor drive is provided that includes a HIM with a...
US-1,028,2284 Test method, system, and device, and readable storage medium
Disclosed are a test method, system, and device, as well as a readable storage medium. The test system is used to: set parameters of a test grid used for grid...
US-1,028,2283 Orchestrating and providing a regression test
A device may receive information associated with an application to be tested. The device may identify test data associated with the application to be tested...
US-1,028,2282 Automated HTTP user flows simulator
A testing method and system for automatic Hypertext Transfer Protocol (HTTP) testing, the system including a memory configured to store sequences of user...
US-1,028,2281 Software testing platform and method
An integrated test accelerator platform that ensures discrete testing solutions to be integrated to work together in harmony, and resources (people, data, and...
US-1,028,2280 Automated scalable video game testing system
A method and system are presented that can model a video game in a state graph. The nodes can be configured to represent actions are performable in the video...
US-1,028,2279 System and method for diagnosing information technology systems in multiple virtual parallel universes
The system and method for diagnosing information technology systems in multiple virtual parallel universes described herein may create virtualized parallel...
US-1,028,2278 Visualization of dependency check outcomes and error resolution
A system, a method, and a computer program product for visualizing an outcome of dependency checks and resolution of errors in various software applications are...
US-1,028,2277 Streams: intelligent operator subset for debug
Techniques are disclosed for identifying a minimal operator subsets in a distributed streams application for debugging purposes. A debugging tool receives a...
US-1,028,2276 Fingerprint-initiated trace extraction
Techniques relate to fingerprint-initiated trace extraction. A determination is made of whether a fingerprint is present in software that is currently executing...
US-1,028,2275 Method and system for managing code
Management of an extensive code database having multiple user tenants building code is provided. A request to check-in code is received, and a build and...
US-1,028,2274 Presenting differences between code entity invocations
Presenting differences between code entity invocations includes identifying a plurality of families of invocations of a code entity. Each family is defined...
US-1,028,2273 Application monitoring using workload metadata
A system for application monitoring includes an interface to receive an indication regarding an application. The system includes a processor to determine...
US-1,028,2272 Operation management apparatus and operation management method
An operation management apparatus for discerning a bottleneck of a system in an execution environment of a migration-destination without operating the system in...
US-1,028,2271 Storage device and method of operating the same
Provided herein may be a storage device and a method of operating the same. In a storage device for controlling operational performance depending on...
US-1,028,2270 Hybrid signal diagnostic method, ID module and process control system using the hybrid signal
A diagnostic method of diagnosing a type of a field device, includes: setting a plurality of connection units included in an I/O module to be in a state of...
US-1,028,2269 Read technique for a bus interface system
Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line....
US-1,028,2268 Software flow execution tracing
In one embodiment, a logging process initiates a trace of an execution flow across a plurality of processes, and creates a log context for the trace, the log...
US-1,028,2267 Monitor peripheral device based on imported data
Various examples described herein provide for monitoring a peripheral device by data imported from the peripheral device. The peripheral data may comprise a...
US-1,028,2266 Apparatus and system for testing touch screen and apparatus for controlling test of touch screen
The present disclosure provides an apparatus and system for testing a touch screen, and an apparatus for controlling test of a touch screen. The apparatus for...
US-1,028,2265 Verifying a graph-based coherency verification tool
Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor...
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