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Patent # Description
US-1,029,0686 Display device and method of manufacturing the same
An aspect of the present invention is directed to a display device including: an array substrate arranged with a plurality of pixels each having a...
US-1,029,0685 Display device
A display device includes: a display panel layer including a display area and a second non-light emitting area, the display area including a plurality of light...
US-1,029,0684 Array substrate, display panel and display apparatus having the same, and fabricating method thereof
The present application discloses an array substrate having a subpixel region and an inter-subpixel region, a display panel and a display apparatus having the...
US-1,029,0683 Organic light emitting display device
Disclosed is an organic light emitting display device including a plurality of unit pixels. The unit pixels includes one or more red sub-pixels, one or more...
US-1,029,0682 3D IC semiconductor device and structure with stacked memory
A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the...
US-1,029,0681 Array of hole-type surround gate vertical field effect transistors and method of making thereof
Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A...
US-1,029,0680 ReRAM MIM structure formation
Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit...
US-1,029,0679 High-Density STT-MRAM with 3D arrays of MTJs in multiple levels of interconnects and method for producing the same
A scalable method of forming an integrated high-density STT-MRAM with a 3D array of multi-level MTJs and the resulting devices are provided. Embodiments include...
US-1,029,0678 Magnetic shielding package structure for MRAM device and method for producing the same
Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided....
US-1,029,0677 Semiconductor device having hall elements formed in a semiconductor substrate and a magnetic body flux concentrator
A semiconductor device includes a semiconductor substrate having a plurality of Hall elements formed therein, and a magnetic body formed on the semiconductor...
US-1,029,0676 Superconducting device with thermally conductive heat sink
An integrated circuit is provided that comprises a resistor, a first superconducting structure coupled to a first end of the resistor, and a second...
US-1,029,0675 Light emitting diode module and method of forming a light emitting diode module
The invention provides an LED module having a concentrated light output window. Light output from a first output window of an LED assembly (e.g. from a...
US-1,029,0674 Engineered substrate including light emitting diode and power circuitry
A gallium nitride based integrated circuit architecture includes a first electronic device including a first set of III-N epitaxial layers and a second...
US-1,029,0673 Bitline settling improvement and FPN reduction by floating bitline during charge transfer
A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating...
US-1,029,0672 Image sensor semiconductor packages and related methods
An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A...
US-1,029,0671 Image sensor device and method of forming same
An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate...
US-1,029,0670 Resonant-filter image sensor and associated fabrication method
A resonant-filter image sensor includes a pixel array including a plurality of pixels and a microresonator layer above the pixel array. The microresonator layer...
US-1,029,0669 Light screening composition
The present invention is to provide a light screening composition that allow forming of a light screening film having excellent adhesiveness to a substrate and...
US-1,029,0668 Image sensors with adjustable pixel density and pixel density adjustment methods thereof
Embodiments of the present application disclose image sensors with adjustable pixel density and pixel density adjustment methods thereof, wherein one of the...
US-1,029,0667 Front-illuminated photosensitive logic cell
Photosensitive logic cell on a semiconductor-on-insulator substrate, possessing a P type transistor and an N type transistor fabricated on the front face of the...
US-1,029,0666 Thin film transistor (TFT) array substrates and manufacturing methods thereof
The present disclosure relates to a thin film transistor (TFT) array substrate and a manufacturing method thereof. The manufacturing method includes adopting a...
US-1,029,0665 Array substrates, display devices, and the manufacturing methods thereof
The present disclosure relates to an array substrate, a display device, and the manufacturing method thereof. The array substrate includes a substrate, and a...
US-1,029,0663 Manufacturing method of thin film transistor and manufacturing method of array substrate
The invention provides a manufacturing method of a thin film transistor and a manufacturing method of an array substrate. A photoresist is used to define a...
US-1,029,0662 Manufacturing method of substrate for display device and manufacturing method of display device
A substrate for a display device, includes: an insulation substrate; an insulation film, which is formed on the insulation substrate and is primarily made of...
US-1,029,0661 Thin film transistor and method of fabricating the same, array substrate and display apparatus
A method of fabricating a TFT includes a step of forming a gate electrode, a gate insulation layer, an active layer, a source electrode, a drain electrode, a...
US-1,029,0660 Array substrate, manufacturing method thereof, display panel and display device
An array substrate, a manufacturing method thereof, a display panel and a display device are provided. The array substrate includes a base substrate, and a gate...
US-1,029,0659 Methods for manufacturing display panels having reduced contact resistance, display panels and display devices
The present disclosure relates to a method for manufacturing a display panel, a display panel and a display device. There is provided a method for manufacturing...
US-1,029,0658 Thin film transistor substrate and display device including the same
Disclosed is a thin film transistor substrate which facilitates to realize a bottom gate structure where a gate electrode is disposed below an active layer, and...
US-1,029,0657 Display device
A display device has a thin film transistor on a substrate. The thin film transistor includes a first transistor having an oxide semiconductor film, a first...
US-1,029,0656 Semiconductor device with oxide semiconductor film electrical characteristic change of which is inhibited
Provided is a transistor which includes an oxide semiconductor film in a channel region. A change from a shift value before light irradiation to a shift value...
US-1,029,0655 Low temperature polysilicon array substrate and method for manufacturing the same
A low temperature polysilicon array substrate and a method for manufacturing the same are disclosed. The method includes forming a light shield layer, a buffer...
US-1,029,0654 Circuit structures with vertically spaced transistors and fabrication methods
Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for...
US-1,029,0653 Integrated circuit layout structure
An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a...
US-1,029,0652 Three-dimensional memory device with graded word lines and methods of making the same
A method of forming a three-dimensional memory device includes providing an alternating stack of insulating layers and sacrificial material layers located...
US-1,029,0651 Semiconductor devices with non-overlapping slits in-between memory blocks
A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first...
US-1,029,0650 Self-aligned tubular electrode portions inside memory openings for drain select gate electrodes in a...
Memory opening fill structures extend through an alternating stack of insulating layers and electrically conductive layers and a combination of an insulating...
US-1,029,0649 Semiconductor device and method for manufacturing same
According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a columnar portion, a hole,...
US-1,029,0648 Three-dimensional memory device containing air gap rails and method of making thereof
An alternating stack of insulating layers and spacer material layers located over a substrate. The spacer material layers are formed as, or are subsequently...
US-1,029,0647 Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of...
A source select level silicon nitride layer and an alternating stack of insulating layers and sacrificial silicon nitride layers are formed over a substrate. A...
US-1,029,0646 Semiconductor device and method of manufacturing the same
A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first channel layers arranged...
US-1,029,0645 Three-dimensional memory device containing hydrogen diffusion barrier layer for CMOS under array architecture...
A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen diffusion...
US-1,029,0644 Non-volatile memory structure and method for preventing non-volatile memory structure from generating program...
A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is...
US-1,029,0643 Three-dimensional memory device containing floating gate select transistor
A three-dimensional memory device includes an alternating stack of insulating layers and control gate electrodes located over a substrate, a drain select gate...
US-1,029,0642 Flash memory devices incorporating a polydielectric layer
Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the...
US-1,029,0641 Semiconductor device
A semiconductor device has a 6T SRAM cell formed on a substrate. The SRAM cell includes a first and a second PMOS transistors formed over an N-well line in a...
US-1,029,0640 Static random access memory cell and static memory circuit
A 6T SRAM cell includes a substrate having thereon a first pull-up (PU-1) transistor, a first pull-down (PD-1) transistor, a second pull-up (PU-2) transistor,...
US-1,029,0639 VNW SRAM with trinity cross-couple PD/PU contact and method for producing the same
A method of forming a VNW SRAM device with a vertical cross-couple/PD/PU contact landed on a PD/PU gate and a bottom nRX and pRX interface and the resulting...
US-1,029,0638 Method of forming dynamic random access memory device
A method of forming dynamic random access memory (DRAM) device, comprises the following steps. First of all, a plurality of active areas is formed in a...
US-1,029,0637 Wrap-around fin for contacting a capacitor strap of a DRAM
A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying...
US-1,029,0636 Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods
A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first...
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