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Patent # Description
US-1,029,0635 Buried interconnect conductor
Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active...
US-1,029,0634 Multiple threshold voltages using fin pitch and profile
A multi-Vt FinFET includes a semiconductor substrate, multiple first fins coupled to the semiconductor substrate having a first fin pitch, and multiple second...
US-1,029,0633 CMOS compatible fuse or resistor using self-aligned contacts
A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure...
US-1,029,0632 AC-coupled switch and metal capacitor structure for nanometer or low metal layer count processes
Alternating Current (AC)-coupled switch and metal capacitor structures for nanometer or low metal layer count processes are provided. According to one aspect of...
US-1,029,0631 Linearity and lateral isolation in a BiCMOS process through counter-doping of epitaxial silicon region
Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type...
US-1,029,0630 BiCMOS integration with reduced masking steps
A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device...
US-1,029,0629 Protective circuit for cathode layer, protective method and OLED display device
A protective circuit for a cathode layer, a protective method and an OLED display device are provided. The protective circuit includes a power supply, and an...
US-1,029,0628 Electrostatic discharge protection circuit
The present application belongs to field of integrated circuit and discloses an electrostatic discharge protection circuit comprising a first N-type transistor...
US-1,029,0627 Embedded high voltage LDMOS-SCR device with a strong voltage clamp and ESD robustness
The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness, which can be used as the on-chip ESD...
US-1,029,0626 High voltage electrostatic discharge (ESD) bipolar integrated in a vertical field-effect transistor (VFET)...
Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a...
US-1,029,0625 Insulated gate semiconductor device
An insulated gate semiconductor device includes a main insulated gate transistor having a gate electrode controlling a main current, a current-detecting...
US-1,029,0624 ESD protection device and method for manufacturing the same
Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial...
US-1,029,0623 Gate input protection for devices and systems comprising high power E-mode GaN transistors
An integrated gate protection device P for a GaN power transistor D1 provides negative ESD spike protection. Protection device P comprises a smaller gate width...
US-1,029,0622 Method for expanding spacings in light-emitting element array
A method for expanding spacings in a light-emitting element array includes the following steps of: providing a light-emitting element array unit including a...
US-1,029,0621 Method of manufacturing a package-on-package type semiconductor package
A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various...
US-1,029,0620 Package with SoC and integrated memory
A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The...
US-1,029,0619 Photonic integrated circuit package
Methods, systems, and apparatus, including a photonic integrated circuit package, including a photonic integrated circuit chip, including an active optical...
US-1,029,0618 Back-to-back stacked dies
Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a...
US-1,029,0617 LED light source comprising an electronic circuit
An electroluminescent light source including light-emitting diodes arranged on a substrate made of silicon. The light source integrates an electronic circuit...
US-1,029,0616 Weld joint with constant overlap area
A packaged semiconductor device has a plurality of leads. A respective lead is to be welded to an electrical coupling that has a substantially rectangular end...
US-1,029,0615 Method and apparatus for improved direct transfer of semiconductor die
A system to effectuate improved transfer of semiconductor die. A first frame secures a first substrate having the semiconductor die. A second frame secures a...
US-1,029,0614 Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency...
System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving...
US-1,029,0613 Multiple bond via arrays of different wire heights on a same substrate
Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires ("first wires") extend from a surface of the substrate....
US-1,029,0612 Systems and methods for flash stacking
A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The Wafers are processed with metallic...
US-1,029,0611 Semiconductor packages and methods of forming same
In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side...
US-1,029,0610 PoP device and method of forming the same
A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a...
US-1,029,0609 Semiconductor device and manufacturing method of the same
Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact...
US-1,029,0608 Signal isolator having bidirectional diagnostic signal exchange
Methods and apparatus for a signal isolator having first and second dies separated by a voltage barrier region, wherein transmit and receive paths of the first...
US-1,029,0607 Method for manufacturing light emitting device including light emitting element and color conversion material layer
A method of manufacturing a light emitting device includes: preparing a light-transmissive member including a light reflective sheet that has a through-hole,...
US-1,029,0606 Interposer with identification system
Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an...
US-1,029,0604 Substrateless integrated circuit packages and methods of forming same
Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed...
US-1,029,0603 High-frequency circuit
A high-frequency circuit includes: a first substrate; a transmission line formed on the first substrate and having first and second output portions branched...
US-1,029,0602 Semiconductor device and method of making semiconductor device
Inexpensive production is achieved while avoiding the degradation of electrical performance caused by the lowering of heat dissipation. The base plate 11 used...
US-1,029,0601 Method of manufacturing bonded body
A method of manufacturing a bonded body in which a first body and a second body are bonded using a glass paste. The glass paste includes a crystallized glass...
US-1,029,0600 Dummy flip chip bumps for reducing stress
A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically...
US-1,029,0599 Conductive pillar shaped for solder confinement
A method of fabricating a pillar-type connection includes forming a second conductive layer on a first conductive layer to define a conductive pillar that...
US-1,029,0598 Method and apparatus for forming backside die planar devices and saw filter
Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the...
US-1,029,0597 Semiconductor device
A semiconductor device according to an embodiment comprises a substrate, an epitaxial layer on the substrate, and a cluster including a plurality of particles...
US-1,029,0596 Semiconductor device having a passivation layer and method of making the same
A method of making a semiconductor device includes depositing a dielectric layer over a conductive pad using a first deposition process. The method further...
US-1,029,0595 Three-dimensional semiconductor memory device and method for manufacturing the same
According to an embodiment, a semiconductor memory device includes a substrate, an insulating film, a plurality of conductive films, an insulating member, a...
US-1,029,0594 Fragmenting computer chips
A method comprising bonding a first substrate to a second substrate. The first substrate includes a layer of one or more pairs of reactive material. The method...
US-1,029,0593 Method of assembling QFP type semiconductor device
A method of assembling QFP devices includes providing a lead frame having leads that extend from a dam bar to a die flag, and performing a first molding process...
US-1,029,0592 Semiconductor package, and a method for forming a semiconductor package
A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the...
US-1,029,0591 Wiring board, electronic device, and electronic module
A wiring board includes an insulating substrate, mount electrodes arranged to face each other on a first main surface of the insulating substrate along a pair...
US-1,029,0590 Stacked semiconductor device and method of manufacturing the same
A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric...
US-1,029,0589 Folding thin systems
A foldable microelectronic assembly and a method for forming the same are provided. One or more packages comprising encapsulated microelectronic elements are...
US-1,029,0588 Ultra-thin semiconductor component fabrication using a dielectric skeleton structure
In one implementation, a method for forming ultra-thin semiconductor components includes fabricating multiple devices including a first device and a second...
US-1,029,0587 Cooler with emi-limiting inductor
A power device package includes a dielectric substrate having an upper conductor layer and a lower conductor layer, a semiconductor die coupled to the upper...
US-1,029,0586 Package substrate with embedded noise shielding walls
A package substrate with embedded noise shielding walls is disclosed. One of the embodiment comprises a signal line S sandwiched by a left shielding wall W1 and...
US-1,029,0585 Shielded module having compression overmold
A method for fabricating a radio-frequency (RF) module is disclosed, the method including forming or providing a first assembly that includes a packaging...
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