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Searching: cpu processor





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Patent # Description
US-9,633,407 CPU/GPU synchronization mechanism
A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a...
US-9,613,393 Closed loop CPU performance control
The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves...
US-9,613,214 Self-measuring nonvolatile memory devices with remediation capabilities and associated systems and methods
Several embodiments of systems incorporating nonvolatile memory devices are disclosed herein. In one embodiment, a system can include a central processor (CPU)...
US-9,612,909 Computer system
A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a...
US-9,612,643 Controlling the CPU slew rates based on the battery state of charge
Methods and apparatus relating to controlling processor slew rates based on battery charge state/level are described. In one embodiment, logic causes...
US-9,606,920 Multi-CPU system and computing system having the same
A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first...
US-9,606,919 Method and apparatus to facilitate shared pointers in a heterogeneous platform
A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous...
US-9,606,913 Electronic circuit for and method of executing an application program stored in a one-time-programmable (OTP)...
A method and apparatus for executing an application program stored in an one-time-programmable, OTP, memory in a system on chip (SoC) is described. The SoC has...
US-9,606,887 Persisting large volumes of data in an efficient unobtrusive manner
Embodiments provide a data persisting mechanism that allows for efficient, unobtrusive persisting of large volumes of data while optimizing the use of system...
US-9,603,774 Evidence-based acupuncture and moxibustion meridian-acupoint treating and detecting instrument supporting...
A multipath-output-supporting evidence-based acupuncture and moxibustion acupoint therapeutic and detecting instrument and a using method thereof. The...
US-9,600,388 Information processing apparatus that computes power consumption for CPU command
An information processing apparatus includes a hardware processor and a memory storing executable instructions that, when executed by the processor, cause the...
US-9,596,111 Methods and apparatus for multi-channel modem and preamble detection
Methods and apparatus for multiple channel modem and preamble detection. In an example arrangement, a system includes a plurality of communication nodes coupled...
US-9,594,659 CPU utilization metering on systems that include multiple hardware threads per core
Indicating usage in a system includes implementing a performance counter associated with one or more hardware threads; counting events associated with the one...
US-9,584,621 Direct cache access for network input/output devices
Methods and systems for improving efficiency of direct cache access (DCA) are provided. According to one embodiment, a set of DCA control settings are defined...
US-9,569,279 Heterogeneous multiprocessor design for power-efficient and area-efficient computing
A technique for managing processor cores within a multi-core central processing unit (CPU) provides efficient power and resource utilization over a wide...
US-9,569,223 Mixed shared/non-shared memory transport for virtual machines
Methods, systems and computer program products are provided for mixed shared/non-shared memory transport in virtual machines. A computer-implemented method may...
US-9,564,918 Real-time reduction of CPU overhead for data compression
Real-time reduction of CPU overhead for data compression is performed by a processor device in a computing environment. Non-compressing heuristics are applied...
US-9,563,588 OS bypass inter-processor interrupt delivery mechanism
The present disclosure provides methods and systems to allow user space applications running on different cores to efficiently communicate interrupts between...
US-9,563,256 Processor hiding its power-up latency with activation of a root port and quickly sending a downstream cycle
Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing...
US-9,558,748 Methods for hybrid GPU/CPU data processing
The present invention describes methods for performing large-scale graph traversal calculations on parallel processor platforms. The invention describes methods...
US-9,558,351 Processing structured and unstructured data using offload processors
A structured data processing system is disclosed that can include a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules...
US-9,558,152 Synchronization method, multi-core processor system, and synchronization system
A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued...
US-9,553,776 System and method for accessing operating system and hypervisors via a service processor of a server
The present disclosure relates to a server that makes use of a host central processing unit (CPU) which accesses a production network to enable communications...
US-9,552,250 Detecting X86 CPU register corruption from kernel crash dumps
Discovering a hardware failure in a processor is disclosed. When an operating system or application fails, a function containing the instruction that failed...
US-9,552,033 Latency-based power mode units for controlling power modes of processor cores, and related methods and systems
Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode...
US-9,550,129 Multiplayer game platform for toys fleet controlled by mobile electronic device
A multi-player game platform comprising: at least one mobile electronic device (MED) comprising a processor and configured to execute programmable commands of a...
US-9,544,451 Multi-core image processor for portable device
A portable handheld device including a CPU for processing a script; a multi-core processor for processing an image; an input buffer for receiving data for...
US-9,542,190 Processor with fetch control for stoppage
A data processor of an embodiment includes a memory, an instruction cache, a processing unit (CPU), and a fetch process control unit. The memory stores a...
US-9,541,992 Method of performing dynamic voltage and frequency scaling operation, application processor performing method,...
A method of performing a dynamic voltage and frequency scaling operation comprises controlling a clock management unit (CMU) to predict an operating state of a...
US-9,535,842 System and method for performing message driven prefetching at the network interface
Each computing node of a distributed computing system may implement a hardware mechanism at the network interface for message driven prefetching of application...
US-9,530,176 Image processing apparatus and method for processing image thereof
An image processing apparatus and image processing method thereof are disclosed. The image processing apparatus includes a first image processor which includes...
US-9,529,750 Service processor (SP) initiated data transaction with bios utilizing interrupt
Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing interrupts. In certain...
US-9,529,410 Service processor (SP) initiated data transaction with BIOS utilizing power off commands
Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing power off commands. In...
US-9,526,026 Method for controlling information processing apparatus and information processing apparatus
A method for controlling an information processing apparatus including a CPU that executes an application relevant to communication other than baseband...
US-9,525,663 Multiple CPU architecture platform network firewall
A system includes a communication processor and an application processor communicatively coupled to the communication processor. The communication processor is...
US-9,523,721 Method and apparatus for precision CPU monitoring
Example embodiments of a processor current monitor include a switching voltage regulator including a series-connected LC filter including a first inductor, with...
US-9,513,939 Agile VM load balancing through micro-checkpointing and multi-architecture emulation
Methods and systems for agile load balancing include detecting an increased load for a first primary virtual machine (VM) on a first node that has a plurality...
US-9,507,938 Real-time code and data protection via CPU transactional memory support
A technique allows for memory bounds checking for dynamically generated code by using transactional memory support in a processor. The memory bounds checking...
US-9,497,086 Computing system with off-load processing for networking related tasks
A method is described that comprises executing a service selection method on an off load processor of a computing system to select an available network service...
US-9,483,626 Multi-security-CPU system
A computing system includes a first security central processing unit (SCPU) of a system-on-a-chip (SOC), the first SCPU configured to execute functions of a...
US-RE46,193 Distributed power control for controlling power consumption based on detected activity of logic blocks
An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller...
US-9,477,295 Non-volatile memory express (NVMe) device power management
Systems and methods for managing power to Non-Volatile Memory Express (NVMe) devices. In some embodiments, an Information Handling System (IHS) may include a...
US-9,471,401 Parallel runtime execution on multiple processors
A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or...
US-9,453,867 Processor chip with ultrasound transducer for ultrasound chip debugging
A transceiver device combination includes a first ultrasound transducer and a processor chip including a central processing unit (CPU). A memory is coupled to...
US-9,449,410 Intra-frame timestamps for tile-based rendering
This disclosure describes techniques for supporting intra-frame timestamps in a graphics system that performs tile-based rendering. The techniques for...
US-9,448,889 BIOS failover update with service processor
Certain aspects direct to basic input/output system (BIOS) failover update with a service processor (SP). In certain embodiments, the system includes a host...
US-9,448,808 BIOS update with service processor without serial peripheral interface (SPI) access
Certain aspects direct to BIOS update with a service processor (SP) without access through a serial peripheral interface (SPI). In certain embodiments, the...
US-9,448,779 Execution of retargetted graphics processor accelerated code by a general purpose processor
One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on...
US-9,436,526 Parallel runtime execution on multiple processors
A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or...
US-9,436,504 Techniques for managing the execution order of multiple nested tasks executing on a parallel processor
One embodiment of the present disclosure sets forth an enhanced way for GPUs to queue new computational tasks into a task metadata descriptor queue (TMDQ)....
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