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Patent # Description
US-1,013,5928 Network interface device having general-purpose computing capability
Techniques for a network interface controller (NIC) capable of performing general-purpose computing tasks without intervention from a central processing unit...
US-1,012,7039 Extension of CPU context-state management for micro-architecture state
A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a...
US-1,012,0773 Estimating processor usage
Methods and systems are disclosed for determining a CPU usage adjustment factor and for automatically applying the CPU usage adjustment factor to provide a CPU...
US-1,011,4679 Logical CPU division usage heat map representation
A logical central processing unit (CPU) division management view is displayed for a device having multiple logical CPU divisions. The management view is...
US-1,010,3956 Virtual machine processor and memory resource coordinator
A network monitor is used to determine resource (e.g., CPU, memory, storage, or network) utilization of one or more virtual machines on one or more...
US-1,010,1977 Method and system of a command buffer between a CPU and GPU
A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes...
US-1,009,1226 Method and apparatus for service traffic security using DIMM channel distribution in multicore processing system
The present invention relates to a multicore communication processing service. More specifically, aspects of the present invention provide a technology for...
US-1,008,9150 Apparatus, device and method for allocating CPU resources
A method of central processor unit (CPU) resource allocation for a multi-processor device includes the step of obtaining the amounts of demanded CPU resources...
US-1,008,3145 Motherboard module having switchable PCI-E lane
A motherboard module having switchable PCI-E lanes includes a CPU, a first PCI-E slot, a second PCI-E slot, a first switch, and a second switch. 1st to a-th...
US-1,008,3068 Fast transfer of workload between multiple processors
Techniques and systems for prescheduling an alternative CPU as soon as a need for a task is detected by a primary CPU are disclosed. A process includes...
US-1,008,2858 Peripheral device assistance in reducing CPU power consumption
A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources,...
US-1,007,8615 Ethernet controller with integrated multi-media payload de-framer and mapper
A method of operation in a system is disclosed. The system includes a system processor, main memory coupled to the system processor, and a serial input/output...
US-1,006,8518 Method, apparatus and system for dithering an image
A method of dithering pixels of a graphical representation is described, the method comprising the steps of receiving the graphical representation which...
US-1,006,1623 Execution of an instruction for performing a configuration virtual topology change
In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest...
US-1,005,5261 Execution of an instruction for performing a configuration virtual topology change
In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest...
US-1,004,2812 Method and system of synchronizing processors to the same computational point
A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first...
US-1,003,1880 Network device and information transmission method
The application provides a network device, which includes: a main control board and a service board, where the main control board includes a processor and a...
US-1,003,1676 Memory controller, and memory module and processor including the same
In a memory controller, a request handler processes a write request which is issued from a CPU and requests data write to a memory device using a phase change...
US-1,002,7760 Methods, systems, and computer readable media for short and long term policy and charging rules function (PCRF)...
A method for assigning new Diameter sessions to policy and charging rules functions (PCRFs) may be performed at a Diameter routing agent including at least one...
US-1,002,6145 Resource sharing on shader processor of GPU
Techniques for allowing for concurrent execution of multiple different tasks and preempted prioritized execution of tasks on a shader processor. In an example...
US-1,002,5741 System-on-chip, mobile terminal, and method for operating the system-on-chip
A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit...
US-1,001,9579 Embedded controller for safety booting and method thereof
A safety booting method for an embedded controller is applied in a laptop. The embedded controller is installed in the laptop, and the laptop includes a central...
US-1,001,3360 Managing reuse information with multiple translation stages
Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor at a first access level and at least...
US-1,001,3298 Enhanced dump data collection from hardware fail modes
An approach is provided for collecting data for diagnosing a failure of a computer hardware device. After an indication of the failure of the computer hardware...
US-1,000,9490 Image forming system, image forming apparatus, and program
An image forming system includes an image forming apparatus and a communication terminal. The image forming apparatus communicates with the communication...
US-1,000,7623 Data processor and control system
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller...
US-1,000,7495 Code generation method for scheduling processors using hook function and exception handling function
A code generating method, a compiler, a scheduling method, an apparatus and a scheduling system where the generated code is an executable code and applied to a...
US-1,000,7464 Method and apparatus for integration of non-volatile memory
Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture...
US-9,996,059 Variable precision thermal sensor
A high accuracy on-chip thermal sensor includes an integrated circuit and sensing elements. The thermal sensor finds application in various mobile and battery...
US-9,991,221 Semiconductor integrated circuit device
A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a...
US-9,990,758 Bounding volume hierarchy generation using a heterogeneous architecture
A system rapidly builds bounding volume hierarchies for ray tracing using both the CPU cores and an integrated graphics processor. The hierarchy is built...
US-9,965,416 DMA controller with arithmetic unit
A digital signal processor (DSP) includes a CPU, and a DMA controller. The DMA controller transfers data from a source to a destination as a function of an...
US-9,952,655 Graphics hardware mode controls
In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator...
US-9,952,650 Hardware apparatus and method for multiple processors dynamic asymmetric and symmetric mode switching
A processing system with multiple processors is switchable between two modes of operation dynamically: symmetrical multi-processing (SMP) and asymmetrical...
US-9,942,179 Schedule based execution with extensible continuation based actions
Generally in a computing environment, executing work based on time (i.e. according to a predetermined schedule) is a common need. However, in cloud based...
US-9,941,007 Solid state drive architectures
A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes...
US-9,935,766 Processor and processor system
A processor includes a CPU core and an encryption processor which includes an address registration region, wherein, after power is supplied, a startup program...
US-9,934,183 Server comprising a plurality of modules
A server (100) having a plurality of modules (1-8), each module including a communication element (16, 26), a plurality of processors (CPU) (10, 11, 20, 21), a...
US-9,929,858 Method and system for detecting fault attacks
In an embodiment, an integrated circuit (IC) device for detecting fault attacks is disclosed. In the embodiment, the IC device includes a main CPU core, memory...
US-9,929,775 Techniques for device-to-device communications
Embodiments of the present disclosure provide apparatuses and systems for proximity communications. The apparatus may include an integrated circuit (IC) package...
US-9,910,801 Processor model using a single large linear registers, with new interfacing signals supporting FIFO-base I/O...
A processor or CPU architecture that implements many enabling technologies proven to enhance data through put supporting the synchronous burst data transfer....
US-9,910,770 Microcomputer having processor capable of changing endian based on endian information in memory
There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing...
US-9,892,481 CPU/GPU synchronization mechanism
A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a...
US-9,886,735 Hybrid engine for central processing unit and graphics processor
A method is described for generating procedural textures for a computer having a unified CPU/GPU memory architecture, to generate textures for contents that are...
US-9,870,473 System and method for security processor control over CPU power states
The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a...
US-9,866,639 Communication apparatus, information processor, communication method, and computer-readable storage medium
According to one embodiment, a communication apparatus communicates with a partner apparatus through a network. The communication apparatus comprises a protocol...
US-9,866,572 Monitoring use of a sensor of a computing device
Monitoring use of a sensor of a computing device. A sensor obtains information from an environment of the computing device. A co-processor provides...
US-9,864,979 Transaction terminal device
When settlement terminal device performs a settlement process with a settlement destination device (for example, an acquirer or a settlement processor),...
US-9,864,629 Real-time code and data protection via CPU transactional memory suppport
A technique allows for memory bounds checking for dynamically generated code by using transactional memory support in a processor. The memory bounds checking...
US-9,852,004 System and method for parallel processing using dynamically configurable proactive co-processing cells
A parallel processing architecture includes a CPU, a task pool populated by the CPU, and a plurality of autonomous co-processing cells each having an agent...
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