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Searching: computer memory





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Patent # Description
US-8,817,711 Method and system for concurrently locating systematic bits and parity bits in physical channel memory to...
A UE receives a HS-PDSCH transmission from a base station and concurrently performs rate matching on systematic bits and parity bits (parity 1 bits, parity 2...
US-8,817,535 Programming method for multi-level cell flash for minimizing inter-cell interference
Systems, methods and computer program products for minimizing floating gate coupling interference and threshold voltage drift associated with flash memory cells...
US-8,817,411 System, method and computer program product for optimization of tape performance
A tape performance optimization method may include accumulating data in a memory, monitoring the accumulation of data, determining whether a certain amount of...
US-8,817,323 Image forming apparatus, image forming method, and computer program product
An image forming apparatus includes: a request signal generating unit that generates a predetermined timing signal and transmits a request signal for a...
US-8,817,110 Instrument card for video applications
Video processing arrangement including a host computer, a video asset coupled to the computer for generating video signals, and an interface for connecting the...
US-8,817,026 Computer hardware architecture and data structures for a ray traversal unit to support incoherent ray traversal
A new hardware architecture defines an indexing and encoding method for accelerating incoherent ray traversal. Accelerating multiple ray traversal may be...
US-8,817,000 Computer-implemented keyboard power management system
A method for displaying power sustainability data for a battery includes providing a processor and a memory device coupled to the processor and receiving power...
US-8,816,325 Scalable quantum computer architecture with coupled donor-quantum dot qubits
A quantum bit computing architecture includes a plurality of single spin memory donor atoms embedded in a semiconductor layer, a plurality of quantum dots...
US-8,814,668 Pari-mutuel wagering system and method
A pari-mutuel wagering system has a gaming computer, a wager database, an account database, and a wager receiving program operably installed in the memory of...
US-8,814,650 Executing multiple applications and their variations in computing environments
Techniques for execution of multiple application programs and their variations are disclosed. One or more individual application program components that are...
US-8,814,624 System and method for toy adoption and marketing
Provided are a method and computer system for providing a virtual world. The computer system includes a virtual product interface system, which includes a...
US-8,814,604 Memory fastening device, computer motherboard and computer
A memory fastening device, a computer motherboard including the memory fastening device and a computer including the computer motherboard are provided. The...
US-RE45,097 High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory...
An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is...
US-8,813,234 Graph-based approach to deterring persistent security threats
A processing device comprises a processor coupled to a memory and implements a graph-based approach to protection of a system comprising information technology...
US-8,813,231 Secure system for allowing the execution of authorized computer program code
Systems and methods for selective authorization of code modules are provided. According to one embodiment, a whitelist containing cryptographic hash values of...
US-8,813,218 Security-enhanced computer systems and methods
In general, the invention provides a computer architecture designed for enhanced data security. In embodiments, the architecture comprises two sub-systems, each...
US-8,813,089 Managing resources for maintenance tasks in computing systems
Systems for managing resources for maintenance tasks in computing systems are provided. One system includes a controller and memory coupled to the controller,...
US-8,813,061 Module updating device
An automobile, vehicle, vessel or other device may include a plurality of modules, software applications, computer program products, controllers or other...
US-8,813,019 Optimized design verification of an electronic circuit
A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of...
US-8,813,018 Method and apparatus for automatically configuring memory size
A logic design system operable to configure an integrated circuit device using custom logic design data is disclosed. The disclosed logic design system includes...
US-8,812,954 Multi-instance, multi-user virtual reality spaces
A multi-instance, multi-user animation platform includes a plurality of modeled parallel dimensions in a computer memory. Each of the parallel dimensions may be...
US-8,812,935 Using a data ECC to detect address corruption
A system for detecting an address or data error in a memory system. During operation, the system stores a data block to an address by: calculating a hash of the...
US-8,812,908 Fast, non-write-cycle-limited persistent memory for secure containers
Techniques for providing fast, non-write-cycle-limited persistent memory within secure containers, while maintaining the security of the secure containers, are...
US-8,812,907 Fault tolerant computing systems using checkpoints
A computer system configured to provide fault tolerance includes a first host system and a second host system. The first host system is programmed to monitor a...
US-8,812,842 Motor vehicle display device, motor vehicle electronic system, motor vehicle, method for displaying data and a...
The invention relates to a motor vehicle display apparatus having an electronic appliance containing: a first memory area (117) for storing data (109),...
US-8,812,818 Management of persistent memory in a multi-node computer system
A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools...
US-8,812,817 Non-blocking data transfer via memory cache manipulation
A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands...
US-8,812,809 Method and apparatus for allocating memory for immutable data on a computing device
One embodiment of the present invention provides a system that allocates memory for immutable data on a computing device. During operation, the system receives...
US-8,812,808 Counter architecture for online DVFS profitability estimation
A counter architecture and a corresponding method are provided for estimating a profitability value of DVFS for a unit of work running on a computing device....
US-8,812,797 Memory controller with external refresh mechanism
The invention relates to a memory controller for use in a System-on-Chip, wherein the System-on-Chip comprises a plurality of agents and an off-chip volatile...
US-8,812,796 Private memory regions and coherence optimizations
Private or shared read-only memory regions. One embodiment may be practiced in a computing environment including a plurality of agents. A method includes acts...
US-8,812,794 Resolving messaging deadlock in a distributed shared memory
Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is...
US-8,812,790 Caching based on spatial distribution of accesses to data storage devices
A controller is communicatively coupled with a storage medium and with a cache device and configured to interface with a processor or a memory of a computer...
US-8,812,774 Memory system and computer program product
According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating...
US-8,812,765 Data coherence method and apparatus for multi-node computer system
A method for maintaining data coherency in a shared-memory computer system having a plurality of nodes divides the local memory of a given node into one or more...
US-8,812,744 Assigning priorities to data for hybrid drives
A hybrid drive includes multiple parts: a performance part (e.g., a flash memory device) and a base part (e.g., a magnetic or other rotational disk drive). A...
US-8,812,694 Dialog establishment over a peer-to-peer architecture
A device and method are described for establishing a dialog between Internet Protocol (IP) end points using a peer-to-peer (P2P) architecture. The device,...
US-8,812,640 Method and system for providing multi-layers item list in browsers with supporting of concurrent multiple users
Supporting end-user to view and operate computing resources by deploying logically organized and graphically represented multi-layered item list ("tree") has...
US-8,812,576 QR decomposition in an integrated circuit device
Circuitry for performing QR decomposition of an input matrix includes multiplication/addition circuitry for performing multiplication and addition/subtraction...
US-8,812,442 Backup service and appliance with single-instance storage of encrypted data
One implementation of a method for providing backup storage services for encrypted data includes receiving signatures of convergently encrypted portions of data...
US-8,812,421 Method and apparatus for autonomous synchronous computing
In accordance with one embodiment, a special purpose computer can be implemented for processing a linear optimization problem capable of being represented in...
US-8,812,400 Managing a memory segment using a memory virtual appliance
In a method for managing a memory segment through use of a memory virtual appliance, data is encapsulated with the memory virtual appliance, in which the memory...
US-8,812,337 Resource allocation based on retail incident information
Security personnel time is assigned to a store property by generating an incident score based on a probability of an incident occurring on a store property. A...
US-8,812,247 Method for achieving improved polypeptide expression
The present invention relates to methods of optimization of a protein coding sequences for expression in a given host cell. The methods apply genetic algorithms...
US-8,812,167 Volt/var switch plan
A power distribution system includes at least one power distribution device and a computer coupled to the power distribution device, wherein the computer...
US-8,812,138 Method and system of controlling and/or configuring an electronic audio recorder, player, processor and/or...
A method and system of controlling and/or configuring an electronic audio processor and/or synthesizer, comprises a network or bi-directional data port that...
US-8,811,902 Data protection system
A protection system includes a storage device and a portable electronic device. The storage device includes a connecting portion, a memory, a first Bluetooth...
US-8,811,758 Lossy compression of data points using point-wise error constraints
A method for compressing a cloud of points with imposed error constraints at each point is disclosed. Surfaces are constructed that approach each point to...
US-8,811,732 Weighted entropy minimization for optimizing a log-chromaticity normal for use in an image process
In a first exemplary embodiment of the present invention, an automated, computerized method is provided for processing an image. According to a feature of the...
US-8,811,453 Dynamic power scaling of an intermediate symbol buffer associated with covariance computations
An intermediate symbol buffer (ISB) configuration and method is provided such that the ISB memory comprises 15 portions, one for each HSDPA spreading code....
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