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Searching: cpu processor





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Patent # Description
US-9,792,157 Execution of an instruction for performing a configuration virtual topology change
In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest...
US-9,785,460 Dynamic virtual machine sizing
A technique is described for managing processor (CPU) resources in a host having virtual machines (VMs) executed thereon. A target size of a VM is determined...
US-9,766,924 Task processor
A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage...
US-9,766,917 Limited virtual device polling based on virtual CPU pre-emption
A hypervisor executing on a computer system identifies a request of a guest operating system of a virtual machine associated with a shared device. The shared...
US-9,760,736 CPU obfuscation for cloud applications
A cloud deployment system is used for obfuscating CPU operation codes in a set of machines operating in a distributed computing environment. A reprogrammable...
US-9,749,207 Methods for measuring physical CPU utilization in a cloud computing infrastructure
Novel techniques are provided to determine concurrent hardware resource usage as expressed in activity performed by hardware processors. A cloud computing...
US-9,749,189 Generating graphical diagram of physical layout of computer platforms
In one aspect, a system includes a service processor (SP), having a processor, a non-volatile memory and a communication interface. The SP receives a component...
US-9,747,221 Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform
A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing...
US-9,747,218 CPU security mechanisms employing thread-specific protection domains
A computer processor includes an instruction processing pipeline that interfaces to a hierarchical memory system employing an address space. The instruction...
US-9,746,898 Systems and methods for controlling processing device power consumption
Systems and methods that may be implemented to decrease power consumption levels of a first processing device (e.g., such as a CPU) based on monitored operating...
US-9,746,897 Method for controlling a multi-core central processor unit of a device establishing a relationship between...
A method for controlling a central processor unit (CPU) of an electronic device includes establishing a corresponding relationship among operational parameters...
US-9,740,866 Automatic measuring boot process using an automatic measuring processor coupled to a memory
An apparatus includes a first interface configured to be coupled to a storage device via a first bus. The apparatus includes a second interface configured to be...
US-9,740,621 Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching,...
Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods...
US-9,734,549 Memory device for providing data in a graphics system and method and apparatus thereof
A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics...
US-9,734,545 Software methods in a GPU
One embodiment of the present invention sets forth a technique for executing a software method within a graphics processing unit (GPU) that minimizes the number...
US-9,734,326 Dynamic interrupt stack protection
A protection unit of an interrupt stack accessible by a CPU controlled by one software program, for storing and removing stack frame(s), the stack protection...
US-9,734,119 Systems and methods for accessing vehicle communications bus information for an application processor
The present application discloses a system and method for accessing vehicle communications bus information outside the bandwidth of a limited CPU without...
US-9,721,322 Selective utilization of graphics processing unit (GPU) based acceleration in database management
A method for the selective utilization of graphics processing unit (GPU) acceleration of database queries in database management is provided. The method...
US-9,710,651 Secure processor for SoC initialization
An embedded system includes an interface to an external peripheral device storing secure boot code and a secure boot controller. The secure boot controller...
US-9,697,059 Virtualized communication sockets for multi-flow access to message channel infrastructure within CPU
A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A...
US-9,680,712 Hardware management and control of computer components through physical layout diagrams
In one aspect, a system includes a service processor (SP), having a processor, a non-volatile memory and a communication interface. The SP receives a component...
US-9,678,813 Method, apparatus, and system for mutual communication between processes of many-core processor
A method, an apparatus, and a system for mutual communication between processes of a many-core processor are provided that relate to the field of many-core...
US-9,668,011 Single chip set-top box system
A single chip set-top box system and method is provided. The system comprises, for example, a transceiver, an audio/video decoder, a CPU, peripherals, DAVIC MAC...
US-9,645,866 Inter-processor communication techniques in a multiple-processor computing platform
This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples,...
US-9,633,407 CPU/GPU synchronization mechanism
A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a...
US-9,613,393 Closed loop CPU performance control
The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves...
US-9,613,214 Self-measuring nonvolatile memory devices with remediation capabilities and associated systems and methods
Several embodiments of systems incorporating nonvolatile memory devices are disclosed herein. In one embodiment, a system can include a central processor (CPU)...
US-9,612,909 Computer system
A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a...
US-9,612,643 Controlling the CPU slew rates based on the battery state of charge
Methods and apparatus relating to controlling processor slew rates based on battery charge state/level are described. In one embodiment, logic causes...
US-9,606,920 Multi-CPU system and computing system having the same
A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first...
US-9,606,919 Method and apparatus to facilitate shared pointers in a heterogeneous platform
A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous...
US-9,606,913 Electronic circuit for and method of executing an application program stored in a one-time-programmable (OTP)...
A method and apparatus for executing an application program stored in an one-time-programmable, OTP, memory in a system on chip (SoC) is described. The SoC has...
US-9,606,887 Persisting large volumes of data in an efficient unobtrusive manner
Embodiments provide a data persisting mechanism that allows for efficient, unobtrusive persisting of large volumes of data while optimizing the use of system...
US-9,603,774 Evidence-based acupuncture and moxibustion meridian-acupoint treating and detecting instrument supporting...
A multipath-output-supporting evidence-based acupuncture and moxibustion acupoint therapeutic and detecting instrument and a using method thereof. The...
US-9,600,388 Information processing apparatus that computes power consumption for CPU command
An information processing apparatus includes a hardware processor and a memory storing executable instructions that, when executed by the processor, cause the...
US-9,596,111 Methods and apparatus for multi-channel modem and preamble detection
Methods and apparatus for multiple channel modem and preamble detection. In an example arrangement, a system includes a plurality of communication nodes coupled...
US-9,594,659 CPU utilization metering on systems that include multiple hardware threads per core
Indicating usage in a system includes implementing a performance counter associated with one or more hardware threads; counting events associated with the one...
US-9,584,621 Direct cache access for network input/output devices
Methods and systems for improving efficiency of direct cache access (DCA) are provided. According to one embodiment, a set of DCA control settings are defined...
US-9,569,279 Heterogeneous multiprocessor design for power-efficient and area-efficient computing
A technique for managing processor cores within a multi-core central processing unit (CPU) provides efficient power and resource utilization over a wide...
US-9,569,223 Mixed shared/non-shared memory transport for virtual machines
Methods, systems and computer program products are provided for mixed shared/non-shared memory transport in virtual machines. A computer-implemented method may...
US-9,564,918 Real-time reduction of CPU overhead for data compression
Real-time reduction of CPU overhead for data compression is performed by a processor device in a computing environment. Non-compressing heuristics are applied...
US-9,563,588 OS bypass inter-processor interrupt delivery mechanism
The present disclosure provides methods and systems to allow user space applications running on different cores to efficiently communicate interrupts between...
US-9,563,256 Processor hiding its power-up latency with activation of a root port and quickly sending a downstream cycle
Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing...
US-9,558,748 Methods for hybrid GPU/CPU data processing
The present invention describes methods for performing large-scale graph traversal calculations on parallel processor platforms. The invention describes methods...
US-9,558,351 Processing structured and unstructured data using offload processors
A structured data processing system is disclosed that can include a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules...
US-9,558,152 Synchronization method, multi-core processor system, and synchronization system
A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued...
US-9,553,776 System and method for accessing operating system and hypervisors via a service processor of a server
The present disclosure relates to a server that makes use of a host central processing unit (CPU) which accesses a production network to enable communications...
US-9,552,250 Detecting X86 CPU register corruption from kernel crash dumps
Discovering a hardware failure in a processor is disclosed. When an operating system or application fails, a function containing the instruction that failed...
US-9,552,033 Latency-based power mode units for controlling power modes of processor cores, and related methods and systems
Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode...
US-9,550,129 Multiplayer game platform for toys fleet controlled by mobile electronic device
A multi-player game platform comprising: at least one mobile electronic device (MED) comprising a processor and configured to execute programmable commands of a...
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