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Searching: cpu processor





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Patent # Description
US-9,541,992 Method of performing dynamic voltage and frequency scaling operation, application processor performing method,...
A method of performing a dynamic voltage and frequency scaling operation comprises controlling a clock management unit (CMU) to predict an operating state of a...
US-9,535,842 System and method for performing message driven prefetching at the network interface
Each computing node of a distributed computing system may implement a hardware mechanism at the network interface for message driven prefetching of application...
US-9,530,176 Image processing apparatus and method for processing image thereof
An image processing apparatus and image processing method thereof are disclosed. The image processing apparatus includes a first image processor which includes...
US-9,529,750 Service processor (SP) initiated data transaction with bios utilizing interrupt
Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing interrupts. In certain...
US-9,529,410 Service processor (SP) initiated data transaction with BIOS utilizing power off commands
Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing power off commands. In...
US-9,526,026 Method for controlling information processing apparatus and information processing apparatus
A method for controlling an information processing apparatus including a CPU that executes an application relevant to communication other than baseband...
US-9,525,663 Multiple CPU architecture platform network firewall
A system includes a communication processor and an application processor communicatively coupled to the communication processor. The communication processor is...
US-9,523,721 Method and apparatus for precision CPU monitoring
Example embodiments of a processor current monitor include a switching voltage regulator including a series-connected LC filter including a first inductor, with...
US-9,513,939 Agile VM load balancing through micro-checkpointing and multi-architecture emulation
Methods and systems for agile load balancing include detecting an increased load for a first primary virtual machine (VM) on a first node that has a plurality...
US-9,507,938 Real-time code and data protection via CPU transactional memory support
A technique allows for memory bounds checking for dynamically generated code by using transactional memory support in a processor. The memory bounds checking...
US-9,497,086 Computing system with off-load processing for networking related tasks
A method is described that comprises executing a service selection method on an off load processor of a computing system to select an available network service...
US-9,483,626 Multi-security-CPU system
A computing system includes a first security central processing unit (SCPU) of a system-on-a-chip (SOC), the first SCPU configured to execute functions of a...
US-RE46,193 Distributed power control for controlling power consumption based on detected activity of logic blocks
An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller...
US-9,477,295 Non-volatile memory express (NVMe) device power management
Systems and methods for managing power to Non-Volatile Memory Express (NVMe) devices. In some embodiments, an Information Handling System (IHS) may include a...
US-9,471,401 Parallel runtime execution on multiple processors
A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or...
US-9,453,867 Processor chip with ultrasound transducer for ultrasound chip debugging
A transceiver device combination includes a first ultrasound transducer and a processor chip including a central processing unit (CPU). A memory is coupled to...
US-9,449,410 Intra-frame timestamps for tile-based rendering
This disclosure describes techniques for supporting intra-frame timestamps in a graphics system that performs tile-based rendering. The techniques for...
US-9,448,889 BIOS failover update with service processor
Certain aspects direct to basic input/output system (BIOS) failover update with a service processor (SP). In certain embodiments, the system includes a host...
US-9,448,808 BIOS update with service processor without serial peripheral interface (SPI) access
Certain aspects direct to BIOS update with a service processor (SP) without access through a serial peripheral interface (SPI). In certain embodiments, the...
US-9,448,779 Execution of retargetted graphics processor accelerated code by a general purpose processor
One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on...
US-9,436,526 Parallel runtime execution on multiple processors
A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or...
US-9,436,504 Techniques for managing the execution order of multiple nested tasks executing on a parallel processor
One embodiment of the present disclosure sets forth an enhanced way for GPUs to queue new computational tasks into a task metadata descriptor queue (TMDQ)....
US-9,436,256 Dynamic CPU voltage regulator phase shedding
A voltage regulator phase shedding system includes one or more subsystems to receive a system management interrupt (SMI), gather processor utilization...
US-9,432,529 Portable handheld device with multi-core microcoded image processor
A portable handheld device includes a CPU for processing a script; a multi-core processor for processing images; and a flash memory connected to the CPU, the...
US-9,419,794 Key management using security enclave processor
An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the...
US-9,418,044 Configuring selected component-processors operating environment and input/output connections based on demand
An entertainment device includes a general-purpose signal processor made up of an assembly of component-processors, each of which can operate in parallel under...
US-9,413,726 Direct cache access for network input/output devices
Methods and systems for improving efficiency of direct cache access (DCA) are provided. According to one embodiment, a set of DCA control settings are defined...
US-9,411,747 Dynamic subroutine stack protection
A protection unit of a subroutine stack accessible by a CPU controlled by one main software program, for storing and removing stack frame(s), the stack...
US-9,411,656 Load balance connections per server in multi-core/multi-blade system
A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further...
US-9,404,970 Debug interface for multiple CPU cores
A system includes processor cores that receive packets over a debug bus. The cores execute transactions in response to the packets. The packets are one of...
US-9,400,696 Execution of real time applications with an automation controller
A method and system are provided for performing the computational execution of automation tasks with automation devices by combining one or more central...
US-9,398,189 Image forming apparatus, and method and program for controlling parallel processing
An image forming apparatus includes a processor including a CPU formed with a plurality of cores, the CPU performing processes, wherein a CPU core managing unit...
US-9,395,999 Microcomputer having processor capable of changing endian based on endian information in memory
There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing...
US-9,395,985 Efficient central processing unit (CPU) return address and instruction cache
A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is...
US-9,390,461 Graphics hardware mode controls
In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator...
US-9,389,910 Paravirtualized migration counter for migrating a virtual CPU to a different physical CPU
An application associated with a virtual processor running on a physical processor reads a first value of a counter and a second value of the counter. The...
US-9,385,970 Method and apparatus for assigning resources in a network node
Achieving resource management within a network processing unit (NPU) can be challenging due to the NPU's fixed and limited instruction set. In the case of large...
US-9,384,050 Scheduling method and scheduling system for multi-core processor system
A scheduling method is executed by a first CPU and a second CPU. The scheduling method includes acquiring by the first CPU and when a first application is...
US-9,372,817 High perfomance DMA controller for video processors
This invention for a VDMA will enable ultra HD resolution (4K) encode/decode at 30 frames per second. This invention maximizes interconnect/DDR utilization and...
US-9,372,734 Outage window scheduler tool
An apparatus for determining a future outage window in which to perform work on a server may include an input for receiving historical performance data about at...
US-9,369,352 Method of capturing server and operating system metrics for virtual to physical topology reporting
A method of improving the accuracy of a topology report, the topology report covering a plurality of operating systems on a plurality of servers, the servers...
US-9,367,494 Data processor and control system
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller...
US-9,367,459 Scheduling method and multi-core processor system
A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when...
US-9,361,259 Integrated circuit with multipurpose processing and for video/audio processing optimization
An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of...
US-9,361,101 Extension of CPU context-state management for micro-architecture state
A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a...
US-9,354,944 Mapping processing logic having data-parallel threads across processors
A method for executing a plurality of data-parallel threads of a processing logic on a processor core includes grouping the plurality of data-parallel threads...
US-9,350,828 Network interface device having general-purpose computing capability
Techniques for a network interface controller (NIC) capable of performing general-purpose computing tasks without intervention from a central processing unit...
US-9,348,657 Method and system of synchronizing processors to the same computational point
A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first...
US-9,342,474 Switching a computer system from a high performance mode to a low power mode
A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a...
US-9,342,384 Function callback mechanism between a central processing unit (CPU) and an auxiliary processor
Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor...
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