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Searching: cpu processor





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Patent # Description
US-9,436,504 Techniques for managing the execution order of multiple nested tasks executing on a parallel processor
One embodiment of the present disclosure sets forth an enhanced way for GPUs to queue new computational tasks into a task metadata descriptor queue (TMDQ)....
US-9,436,256 Dynamic CPU voltage regulator phase shedding
A voltage regulator phase shedding system includes one or more subsystems to receive a system management interrupt (SMI), gather processor utilization...
US-9,432,529 Portable handheld device with multi-core microcoded image processor
A portable handheld device includes a CPU for processing a script; a multi-core processor for processing images; and a flash memory connected to the CPU, the...
US-9,419,794 Key management using security enclave processor
An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the...
US-9,418,044 Configuring selected component-processors operating environment and input/output connections based on demand
An entertainment device includes a general-purpose signal processor made up of an assembly of component-processors, each of which can operate in parallel under...
US-9,413,726 Direct cache access for network input/output devices
Methods and systems for improving efficiency of direct cache access (DCA) are provided. According to one embodiment, a set of DCA control settings are defined...
US-9,411,747 Dynamic subroutine stack protection
A protection unit of a subroutine stack accessible by a CPU controlled by one main software program, for storing and removing stack frame(s), the stack...
US-9,411,656 Load balance connections per server in multi-core/multi-blade system
A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further...
US-9,404,970 Debug interface for multiple CPU cores
A system includes processor cores that receive packets over a debug bus. The cores execute transactions in response to the packets. The packets are one of...
US-9,400,696 Execution of real time applications with an automation controller
A method and system are provided for performing the computational execution of automation tasks with automation devices by combining one or more central...
US-9,398,189 Image forming apparatus, and method and program for controlling parallel processing
An image forming apparatus includes a processor including a CPU formed with a plurality of cores, the CPU performing processes, wherein a CPU core managing unit...
US-9,395,999 Microcomputer having processor capable of changing endian based on endian information in memory
There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing...
US-9,395,985 Efficient central processing unit (CPU) return address and instruction cache
A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is...
US-9,390,461 Graphics hardware mode controls
In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator...
US-9,389,910 Paravirtualized migration counter for migrating a virtual CPU to a different physical CPU
An application associated with a virtual processor running on a physical processor reads a first value of a counter and a second value of the counter. The...
US-9,385,970 Method and apparatus for assigning resources in a network node
Achieving resource management within a network processing unit (NPU) can be challenging due to the NPU's fixed and limited instruction set. In the case of large...
US-9,384,050 Scheduling method and scheduling system for multi-core processor system
A scheduling method is executed by a first CPU and a second CPU. The scheduling method includes acquiring by the first CPU and when a first application is...
US-9,372,817 High perfomance DMA controller for video processors
This invention for a VDMA will enable ultra HD resolution (4K) encode/decode at 30 frames per second. This invention maximizes interconnect/DDR utilization and...
US-9,372,734 Outage window scheduler tool
An apparatus for determining a future outage window in which to perform work on a server may include an input for receiving historical performance data about at...
US-9,369,352 Method of capturing server and operating system metrics for virtual to physical topology reporting
A method of improving the accuracy of a topology report, the topology report covering a plurality of operating systems on a plurality of servers, the servers...
US-9,367,494 Data processor and control system
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller...
US-9,367,459 Scheduling method and multi-core processor system
A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when...
US-9,361,259 Integrated circuit with multipurpose processing and for video/audio processing optimization
An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of...
US-9,361,101 Extension of CPU context-state management for micro-architecture state
A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a...
US-9,354,944 Mapping processing logic having data-parallel threads across processors
A method for executing a plurality of data-parallel threads of a processing logic on a processor core includes grouping the plurality of data-parallel threads...
US-9,350,828 Network interface device having general-purpose computing capability
Techniques for a network interface controller (NIC) capable of performing general-purpose computing tasks without intervention from a central processing unit...
US-9,348,657 Method and system of synchronizing processors to the same computational point
A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first...
US-9,342,474 Switching a computer system from a high performance mode to a low power mode
A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a...
US-9,342,384 Function callback mechanism between a central processing unit (CPU) and an auxiliary processor
Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor...
US-9,342,362 Service-processor-centric computer architecture and method of operation thereof
A computer system and a method of operating a service-processor-centric computer system. In one embodiment, the computer system includes: (1) a CPU configured...
US-9,342,350 System for selecting a task to be executed according to an output from a task control circuit
The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided...
US-9,336,557 Apparatus and methods for processing of media signals
Methods and apparatus for processing media signals. In one embodiment, a data processing device processes fixed and variable rate data using a first and second...
US-9,335,982 Processor emulation using multiple translations
Examples described herein emulate a processing architecture using multiple translations of the same source binary. A first translation binary includes compiler...
US-9,323,314 System and method for reducing energy usage in a mobile communications device
A mobile communications device and a method for reducing energy usage in a mobile communications device are provided. An example mobile communications device...
US-9,323,307 Active display processor sleep state
Power consumption and dissipation is reduced during active display of content from an internal display buffer using a power supply topology that powers a...
US-9,317,090 Methods and apparatuses for operating a data processing system
Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system...
US-9,310,863 Multi-purpose power controller and method
The present invention provides a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size...
US-9,307,054 Intelligent network interface system and method for accelerated protocol processing
A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with...
US-9,304,834 Parallel runtime execution on multiple processors
A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or...
US-9,304,806 Provisioning virtual CPUs using a hardware multithreading parameter in hosts with split core processors
A cloud manager monitors available resources on host computer systems, including a number of hardware threads supported by CPUs on the host computer systems and...
US-9,304,805 Provisioning virtual CPUs using a hardware multithreading parameter in hosts with split core processors
A cloud manager monitors available resources on host computer systems, including a number of hardware threads supported by CPUs on the host computer systems and...
US-9,304,794 Virtual machine control method and virtual machine system using prefetch information
Provided is a virtual machine including a first virtualization module operating on a physical CPU, for providing a first CPU, and a second virtualization module...
US-9,298,768 System and method for the parallel execution of database queries over CPUs and multi core processors
The invention relates to a system for parallel execution of database queries over one or more Central Processing Units (CPUs), and one or more Multi Core...
US-9,295,910 Methods, apparatus and systems for use of a non-native chipset to play original video game cartridges
Apparatus, methods and systems using a more powerful, but non-native, modern CPU/GPU chipset to play one or more types of original console games. The apparatus,...
US-9,292,342 Schedule based execution with extensible continuation based actions
Generally in a computing environment, executing work based on time (i.e. according to a predetermined schedule) is a common need. However, in cloud based...
US-9,288,334 Modem with voice processing capability
A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far...
US-9,286,216 3DIC memory chips including computational logic-in-memory for performing accelerated data processing
This disclosure relates to a three-dimensional (3D) integrated circuit (3DIC) memory chip including computational logic-in-memory (LiM) for performing...
US-9,280,473 Method and apparatus for accessing physical memory from a CPU or processing element in a high performance manner
A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor...
US-9,275,733 Methods and systems for mapping a peripheral function onto a legacy memory interface
A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and...
US-9,270,697 Hardware-assisted integrity monitor
A hardware-assisted integrity monitor may include one or more target machines and/or monitor machines. A target machine may include one or more processors,...
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