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Searching: cpu processor





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Patent # Description
US-7,461,376 Dynamic resource management system and method for multiprocessor systems
A dynamic workload management system enables system administrators to easily identify installed applications and to assign them to affinity groupings in order of...
US-7,461,109 Method and apparatus for providing packed shift operations in a processor
A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing...
US-7,460,550 Storage structure and method utilizing multiple protocol processor units
A storage structure and method having multiple protocol processor units are disclosed. The storage structure comprises a host CPU, a main memory, a storage...
US-7,457,920 Method and system for cache eviction
The proposed system and associated algorithm when implemented improves the processor cache miss rates and overall cache efficiency in multi-core environments in...
US-7,454,550 Systems and methods for providing co-processors to computing systems
Computing systems with conventional CPUs coupled to co-processors or accelerators implemented in FPGAs (Field Programmable Gate Arrays). One embodiment of the...
US-7,454,547 Data exchange between a runtime environment and a computer firmware in a multi-processor computing system
A method, system, apparatus, and computer-readable medium for exchanging data between an application program and a firmware in a computer system having multiple...
US-7,451,332 Methods and apparatuses for controlling the temperature of a data processing system
Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system...
US-7,451,073 System and method for increasing performance in multi-CPU simulation
A system and method for increasing performance in a simulator environment operable to simulate a multiprocessor platform with program code running thereon. A set...
US-7,446,775 Data processor and graphic data processing device
An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a...
US-7,444,630 Method and apparatus for changing microcode to be executed in a processor
A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory...
US-7,433,974 Vehicle computer system with audio entertainment system
A vehicle computer system has an audio entertainment system implemented in a logic unit and audio digital signal processor (DSP) independent from the host CPU....
US-7,429,983 Packet-based digital display system
An all-digital display system includes an electronic processor that is operable to receive an internet protocol video packet and to generate a control signal...
US-7,428,661 Test and debug processor and method
A test and debug processor capable of initiating, commanding and executing JTAG-bus functions without the involvement of an external CPU. The processor includes...
US-7,428,485 System for yielding to a processor
An apparatus, program product and method for coordinating the distribution of CPUs as among logically-partitioned virtual processors. A virtual processor may...
US-7,415,702 Method for zero overhead switching of alternate algorithms in a computer program
A system wherein a Caller Application is enabled to reduce latency after a First Call to a Data Link Library after which a stub function provides direct access...
US-7,415,576 Data processor with block transfer control
A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a...
US-7,406,688 Parallel process execution method and multiprocessor computer
A parallel process execution method that allocates CPU time to parallel processes at any desired ratios. The method sets a time allocation ratio to determine how...
US-7,406,583 Autonomic computing utilizing a sequestered processing resource on a host CPU
An autonomic computing environment is provided by sequestering one of a plurality of processor resources, partitioning a memory, and hiding an input/output (I/O)...
US-7,406,557 Programmable logic device including programmable interface core and central processing unit
A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface...
US-7,404,047 Method and apparatus to improve multi-CPU system performance for accesses to memory
Methods and apparatuses for improving processor performance in a multi-processor system by optimizing accesses to memory. Processors can track the state of a...
US-RE40,437 Thermostat system with remote data averaging
A thermostat system according to the invention includes: a central control device (typically a programmable thermostat with a processor having: a CPU, real time...
US-7,395,409 Split embedded DRAM processor
A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural...
US-7,395,358 Intelligent storage engine for disk drive operations with reduced local bus traffic
For attached disk drive operations such a file copy and move, as well as more elaborate processes such as searching, virus-scanning and volume merge, a novel...
US-7,392,399 Methods and systems for efficiently integrating a cryptographic co-processor
A method and system of processing a cryptographic packet includes receiving a first cryptographic packet in a host CPU. A first set of data required to execute...
US-7,388,682 Image processing method and apparatus, printing method and apparatus, image printing system and method and...
An image printing system which enables printing after setting for printing in detail, even in case of an equipment connected to an interface pursuant to the IEEE...
US-7,383,428 Method, apparatus and computer program product for implementing atomic data tracing
A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit...
US-7,383,426 Processor employing loadable configuration parameters to reduce or eliminate setup and pipeline delays in a...
A deep-pipeline system substantially reduces the overhead of setup delays and pipeline delays by dynamically controlling access of a plurality of configuration...
US-7,383,412 On-demand memory synchronization for peripheral systems with multiple parallel processors
On-demand memory synchronization is provided for peripheral subsystems, including graphics systems, that include multiple co-processors operating in parallel. A...
US-7,380,101 Architecture for a processor complex of an arrayed pipelined processing engine
A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor...
US-7,379,475 Communications processor
A communication processor of a class, such as an Internet tuner, provides such desirable features (FIG. 2) as LAN support, an SPI interface (128), a dedicated...
US-7,376,819 Data processor with selectable word length
An apparatus and method for selecting whether a central processing unit (CPU) performs instruction reading in units of 16 bits (a first word length) or in units...
US-7,374,100 Mobile terminal having smart card coupled with RFID tag and method for performing RFID function in such mobile...
Disclosed is a mobile terminal equipped with a smart card coupled with an RFID tag and a method for performing an RFID function in the mobile terminal. The smart...
US-7,373,447 Multi-port processor architecture with bidirectional interfaces between busses
A multi-port processor architecture having a first bus, a second bus and a central processing unit. The central processing unit having a first and second ports...
US-7,372,741 Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile...
A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality...
US-7,369,938 Navigation system having means for determining a route with optimized consumption
A navigation system of a motor vehicle has an input unit, a position-determining unit, a central processor unit (CPU) for calculating a route between a first and...
US-7,366,814 Heterogeneous multiprocessor system and OS configuration method thereof
Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor...
US-7,363,481 Information processing method for controlling the function of a plurality of processors, program for realizing...
There is provided an information processing method characterized in that, in accordance with an instruction from a host CPU 411, either a CPU 103 or 104 loads a...
US-7,361,083 Multimedia system and method for remote monitoring or refereeing in dart machines
A system and method which comprises a plurality of amusement machines (i.e., video games, flipper games, pinball machines, prize dispensing games, arcade games,...
US-7,360,109 Measuring the interval of a signal using a counter and providing the value to a processor
The present invention aims to be capable of properly measuring the cycle of an external signal even where a timer clock and a CPU clock are operated...
US-7,360,027 Method and apparatus for initiating CPU data prefetches by an external agent
An arrangement is provided for an external agent to initiate data prefetches from a system memory to a cache associated with a target processor, which needs the...
US-7,356,686 Initialization of range registers within chipsets on spare processor cells
A distributed computer system is composed of a plurality of cells, a service processor, and first and second modules. Each of the cells includes a CPU, a memory,...
US-7,355,601 System and method for transfer of data between processors using a locked set, head and tail pointers
A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to...
US-7,352,482 Apparatus and method for processing data and printing the same, and recording medium
A data processor has a plurality of data transmitters, a CPU (divider) for dividing print data into a plurality of data segments and I/O controllers for...
US-7,350,039 Processing controller, data processor, processing controlling method, program thereof and recording medium...
A CPU 290 of a recording/reproducing device 200 acquires automatic video recording request information, and generates, based on EPG data previously acquired, new...
US-7,346,701 System and method for TCP offload
Aspects of the invention may comprise receiving an incoming TCP packet at a TEEC and processing at least a portion of the incoming packet once by the TEEC...
US-7,346,682 System for creating and distributing prioritized list of computer nodes selected as participants in a...
The present invention provides a system and apparatus for efficient and reliable, control and distribution of data files or portions of files, applications, or...
US-7,337,241 Fast-path apparatus for receiving data corresponding to a TCP connection
A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with...
US-7,334,118 Method for resetting a processor involves receiving CPU reset trigger signal from BIOS
A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is...
US-7,334,114 Real-time monitoring, alignment, and translation of CPU stalls or events
A system and method of tracing a group of processor events in real-time in order to enable a programmer to debug and profile the operation and execution of code...
US-7,333,116 Data processor having unified memory architecture using register to optimize memory access
In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an...
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