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Searching: cpu processor





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Patent # Description
US-7,325,144 Portable information processor having password code checking function
Switching between a requiring mode and a non-requiring mode of password code checking is enabled by an IC card with a CPU for accessing an EEPROM. The general...
US-7,325,085 Motherboard and control method thereof
A motherboard includes a south-bridge chipset, a north-bridge chipset and a central processor unit (CPU). The south-bridge chipset generates at least...
US-7,321,945 Interrupt control device sending data to a processor at an optimized time
An interrupt control device for issuing interrupts to a central processing unit (CPU) includes an object acquiring unit for acquiring data or resource(s) for use...
US-7,318,164 Conserving energy in a data processing system by selectively powering down processors
One or more processors are activated and deactivated responsive to processing activity in order to meet a performance or response requirement. Hardware...
US-7,313,665 Multi-Processor data verification components for security modules
The aim of this invention is to improve in an optimal way the security of smart cards to prevent the fraudulent control of a cryptographic processor(s) by means...
US-7,307,667 Method and apparatus for an integrated high definition television controller
A method and an apparatus for an integrated high definition television controller are described. The integrated high definition digital television controller...
US-7,305,544 Interleaved boot block to support multiple processor architectures and method of use
A flash memory has an interleaved boot block compatible with multiple processor architectures. The interleaved boot block may include one boot block compatible...
US-7,302,462 Framework and methods for dynamic execution of digital data processor resources
The invention provides, in one aspect, an improved digital data processing system of the type having a plurality of execution resources, including a central...
US-7,296,271 Replaceable scheduling algorithm in multitasking kernel
Disclosed is providing one of a plurality of schedulers for a multitasking system for a processor that includes choosing a particular one of the schedulers,...
US-7,296,169 Method for adjusting a front-side bus frequency based on a processor usage rate stored in a translation table...
A method for dynamically adjusting central processing unit (CPU) frequency. Firstly, a translation table is provided between multi-layer of CPU usage percentage...
US-7,293,207 Method for testing memory in a computer system utilizing a CPU with either 32-bit or 36-bit memory addressing
A method is provided for testing the entire memory address range of memory in a computer system having a Cpu supporting 32-bit or 36-bit memory addressing. If...
US-7,290,161 Reducing CPU and bus power when running in power-save modes
A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined...
US-7,289,326 Direct contact cooling liquid embedded package for a central processor unit
A direct contact cooling liquid embedded package design for use with a computer central processor unit is suitable for thermal management of high heat...
US-7,287,147 Configurable co-processor interface
A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer...
US-7,284,070 TCP offload network interface device
A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with...
US-7,272,417 Systems and methods for implementing fully redundant antenna hopping with multi-carrier power amplifiers and...
A Transmit Diversity Redundancy controller dynamically mediates implementation of diversity and antenna hopping by detecting and remediating faults on antenna...
US-7,271,841 Method for deinterlacing interlaced video by a graphics processor
A method for deinterlacing interlaced video using a graphics processor includes receiving at least one instruction for a 2D/3D engine to facilitate creation of...
US-7,268,785 System and method for interfacing graphics program modules
A system and method for interfacing graphics program modules written to execute on a plurality of functional units of a graphics processor using a shared memory....
US-RE39,837 Method and apparatus for adjusting a power consumption level based on the amount of time a processor clock is...
A power management mechanism for use in a computer system having a bus, a memory for storing data and instructions, and a central processing unit (CPU). The CPU...
US-7,266,632 Programmable logic device including programmable interface core and central processing unit
A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface...
US-7,260,640 System and method for providing an enhanced enterprise streaming media server capacity and performance
Streaming media servers are used to provide data streams of streaming media data to network devices across a communications network. In order to allow the...
US-7,257,816 Digital data processing apparatus and methods with dynamically configurable application execution on...
The invention provides, in one aspect, an improved digital data processing system of the type having a plurality of execution resources, including a central...
US-7,257,661 Scalable home control platform and architecture
A home-control platform and architecture includes a plurality of serial buses that provide communications among processing devices that are connected to the...
US-7,256,817 Following device
In the following device, at the time of pan/tilt movement of a pan head, images #1 to #3 for three frames shot by a camera are sequentially taken in into an...
US-7,256,789 Programmable display device
It comprises a main CPU, a main memory for storing the programs, display data and other data, a data processing circuit for performing a processing to convert...
US-7,255,284 Smart card and method for controlling a mixed mode thereof
A mixed mode smart card is disclosed including an internal circuit having a CPU, a contactless mode processor adapted to prosecute a contactless mode operation,...
US-7,254,766 Discrete multi-tone (DMT) system and method that communicates a data pump data stream between a general purpose...
The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general...
US-7,254,746 Method and apparatus for using a fault tolerant memory in processor testing and design
An apparatus and method for controlling and providing a robust, single entry cache memory is described in connection with an on-board cache memory integrated...
US-7,245,272 Continuous graphics display for dual display devices during the processor non-responding period
The present invention provides an image/graphics data display mechanism for continuously displaying image/graphics data on dual display devices of a computer...
US-7,243,208 Data processor and IP module for data processor
In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P0), which is...
US-7,237,099 Multiprocessor system having a plurality of control programs stored in a continuous range of addresses of a...
A multiprocessor system has a plurality of CPUs with respective local buses, and a memory which stores a plurality of programs to be executed by the CPUs and is...
US-7,237,036 Fast-path apparatus for receiving data corresponding a TCP connection
A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with...
US-7,234,008 Method and system for exchanging data between a central processing unit and an input/output processor
A method is disclosed for exchanging data between a central processing unit (CPU) and an input/output processor (IOP). The CPU and IOP may both be senders or...
US-7,228,393 Memory interleaving
A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash...
US-7,219,254 Method and apparatus for high availability distributed processing across independent networked computer fault...
A plurality of local network groups of computers (102) are coupled together by a network (104). Independent processing systems that execute a single operating...
US-7,219,245 Adaptive CPU clock management
A method and system for efficiently managing power consumption in a digital processor controls the CPU clock rate based on actual CPU workload by monitoring a...
US-7,216,003 Hi-accuracy three-dimensional topographic modeling apparatus
A cutting apparatus includes a hi-accuracy three-dimensional cutting apparatus for topographic modeling that is electronically coupled with a computer. The...
US-7,206,950 Processor system, instruction sequence optimization device, and instruction sequence optimization program
To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a flag detecting section...
US-7,203,809 Data transfer control method, and peripheral circuit, data processor and processing system for the method
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a...
US-7,200,763 Method and apparatus for controlling the power consumption of a semiconductor device
A method and apparatus are provided for controlling the power consumption of a semiconductor device such as a CPU or other form of processor that is operable to...
US-7,194,614 Boot swap method for multiple processor computer systems
A boot swap method for multiple processor computer systems utilizes a baseboard management controller (BMC) to manage the abnormal booting problem of multiple...
US-7,194,599 Configurable co-processor interface
A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer...
US-7,194,517 System and method for low overhead message passing between domains in a partitioned server
A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a...
US-7,193,846 CPU fan assembly
An apparatus and method for cooling heat generating components within a compartment are disclosed. A cooling assembly isolates heat produced by a processor in a...
US-7,191,241 Fast-path apparatus for receiving data corresponding to a TCP connection
A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with...
US-7,188,199 DMA controller that restricts ADC from memory without interrupting generation of digital words when CPU...
DMA controller for mixed signal device. A mixed signal integrated circuit with memory control is disclosed. A data conversion circuit is provided that is...
US-7,185,500 Active cooling system for CPU
A cooling system for cooling a processor installed within a computer case, the active cooling system comprising: (i) a TEC/heat-sink assembly comprising a...
US-7,185,179 Architecture of a parallel computer and an information processing unit using the same
A computer system provides distributed memory computer architecture achieving extremely high speed parallel processing, and includes: a CPU modules, a plurality...
US-7,178,130 Digital processing architecture using compiled dataflow definition
A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to...
US-7,174,457 System and method for authenticating an operating system to a central processing unit, providing the CPU/OS...
A general-purpose processor (CPU) is configured with a new mechanism facilitating an authenticated boot sequence that provides building blocks for client-side...
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