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Searching: cpu processor





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Patent # Description
US-7,234,008 Method and system for exchanging data between a central processing unit and an input/output processor
A method is disclosed for exchanging data between a central processing unit (CPU) and an input/output processor (IOP). The CPU and IOP may both be senders or...
US-7,228,393 Memory interleaving
A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash...
US-7,219,254 Method and apparatus for high availability distributed processing across independent networked computer fault...
A plurality of local network groups of computers (102) are coupled together by a network (104). Independent processing systems that execute a single operating...
US-7,219,245 Adaptive CPU clock management
A method and system for efficiently managing power consumption in a digital processor controls the CPU clock rate based on actual CPU workload by monitoring a...
US-7,216,003 Hi-accuracy three-dimensional topographic modeling apparatus
A cutting apparatus includes a hi-accuracy three-dimensional cutting apparatus for topographic modeling that is electronically coupled with a computer. The...
US-7,206,950 Processor system, instruction sequence optimization device, and instruction sequence optimization program
To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a flag detecting section...
US-7,203,809 Data transfer control method, and peripheral circuit, data processor and processing system for the method
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a...
US-7,200,763 Method and apparatus for controlling the power consumption of a semiconductor device
A method and apparatus are provided for controlling the power consumption of a semiconductor device such as a CPU or other form of processor that is operable to...
US-7,194,614 Boot swap method for multiple processor computer systems
A boot swap method for multiple processor computer systems utilizes a baseboard management controller (BMC) to manage the abnormal booting problem of multiple...
US-7,194,599 Configurable co-processor interface
A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer...
US-7,194,517 System and method for low overhead message passing between domains in a partitioned server
A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a...
US-7,193,846 CPU fan assembly
An apparatus and method for cooling heat generating components within a compartment are disclosed. A cooling assembly isolates heat produced by a processor in a...
US-7,191,241 Fast-path apparatus for receiving data corresponding to a TCP connection
A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with...
US-7,188,199 DMA controller that restricts ADC from memory without interrupting generation of digital words when CPU...
DMA controller for mixed signal device. A mixed signal integrated circuit with memory control is disclosed. A data conversion circuit is provided that is...
US-7,185,500 Active cooling system for CPU
A cooling system for cooling a processor installed within a computer case, the active cooling system comprising: (i) a TEC/heat-sink assembly comprising a...
US-7,185,179 Architecture of a parallel computer and an information processing unit using the same
A computer system provides distributed memory computer architecture achieving extremely high speed parallel processing, and includes: a CPU modules, a plurality...
US-7,178,130 Digital processing architecture using compiled dataflow definition
A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to...
US-7,174,457 System and method for authenticating an operating system to a central processing unit, providing the CPU/OS...
A general-purpose processor (CPU) is configured with a new mechanism facilitating an authenticated boot sequence that provides building blocks for client-side...
US-7,174,393 TCP/IP offload network interface device
A system for protocol processing in a computer network has a TCP/IP Offload Network Interface Device (TONID) associated with a host computer. The TONID provides...
US-7,174,311 Method and system for text data management and processing
A method and system for delivering programmed textual and graphical material to computer network based users includes a central computer system including...
US-7,171,631 Method and apparatus for jump control in a pipelined processor
An improved method and apparatus for controlling and implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor....
US-7,171,546 CPU life-extension apparatus and method
A CPU life-extension apparatus and method makes a processor appear to be an upgraded CPU to substantially all software applications accessed thereby, thereby...
US-7,170,968 CT scanner system and method for improved positioning
The CT scanning system of the present invention includes a source and detector mounted to a c-arm. The c-arm is positioned on a mounting plate and ball screw to...
US-7,168,074 Runtime prediction framework for CPU intensive applications
A scaled-down representation of input to a compute-intensive application is created. A computing requirement based on the scaled-down representation is...
US-7,167,949 Multi-processor type storage control apparatus for performing access control through selector
A storage control apparatus is coupled to a central processing unit (CPU) and a storage unit to control input/output of data between the CPU and the storage...
US-7,167,926 TCP/IP offload network interface device
An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a...
US-7,162,616 Floating point unit pipeline synchronized with processor pipeline
An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the...
US-7,162,426 Computer motherboard architecture with integrated DSP for continuous and command and control speech processing
The invention is essentially a motherboard design for personal computers which uses DSP hardware in conjunction with a general or specific purpose CPU to process...
US-7,161,904 System and method for hierarchical metering in a virtual router based network switch
A virtual routing platform includes a line interface a plurality of virtual routing engines (VREs) to identify packets of different packet flows and perform a...
US-7,159,766 Peripheral device feature allowing processors to enter a low power state
If a USB device is turned off or is not active, the device may be electrically disconnected from a USB host controller. The device may be electrically...
US-7,159,059 Ultra-modular processor in lattice topology
A Modular Operating Topology Element (MOTE), within a software-latticed network, implements ultra-concurrent operation of a plurality of such MOTEs, as single...
US-7,155,604 Game system having selectable startup display image wherein system processor selects between internal display...
There is disclosed a method of starting up an information processing apparatus which is capable of introducing a variety of elements into an image that is...
US-7,154,399 System and method for determining whether a resident is at home or away
A system and method for monitoring whether a resident is away from home or inactive within the home. A sensor, which includes a transmitter, a processor, a...
US-7,152,027 Reconfigurable test system
A reconfigurable test system including a host computer coupled to a reconfigurable test instrument. The reconfigurable test instrument includes reconfigurable...
US-7,149,918 Method and apparatus for high availability distributed processing across independent networked computer fault...
A plurality of local network groups of computers (102) are coupled together by a network (104). Independent processing systems that execute a single operating...
US-7,139,849 Semiconductor integrated circuit device
A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec...
US-7,139,222 System and method for protecting the location of an acoustic event detector
A system and method for protecting sensor positions in an array of acoustic sensors which make up a gunfire locator system. The inventive system includes a...
US-7,137,036 Microcontroller having an error detector detecting errors in itself as well
A microcontroller including a CPU (Central Processor Unit) is capable of detecting the error of its structural part. The CPU executes a first initialization...
US-7,137,029 Information processor
An information processor is provided with: two chip sets that are each provided with a serial controller, these chip sets being the interface between a CPU and...
US-7,134,046 Method and apparatus for high availability distributed processing across independent networked computer fault...
A plurality of local network groups of computers (102) are coupled together by a network (104). Independent processing systems that execute a single operating...
US-7,134,036 Processor core clock generation circuits
An invention is provided for generating custom clock frequencies within a processor core. A CPU clock signal propagates through a DLL circuit. Further, a control...
US-7,133,944 Media access controller with power-save mode
There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by...
US-7,133,450 Method and devices for digital video signal compression and multi-screen process by multi-thread scaling
The present invention relates to methods and devices for compression and multi-screen process of digital video signals by multi-thread scaling. The method...
US-7,130,425 Method and apparatus for providing a bus-encrypted copy protection key to an unsecured bus
A copy protection (CP) key used by a sending source, such as a POD, to encrypt content such as audio and/or video information is derived by a first key generator...
US-7,127,637 Method and apparatus for high availability distributed processing across independent networked computer fault...
A plurality of local network groups of computers (102) are coupled together by a network (104). Independent processing systems that execute a single operating...
US-7,124,376 Design tool for systems-on-a-chip
A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression,...
US-7,123,190 Skipping z-counts and accurate time in GPS receivers
A navigation-satellite receiver comprises high-sensitivity radio frequency front-end and navigation processor associated with a client CPU. The client CPU runs...
US-7,120,789 System and method for portable on-demand central processing unit
A method and a system for providing a processor to a computer system through a removable CPU module. The processor on the removable CPU module may be shared by...
US-7,118,483 Modular CPU enclosure for gaming machines
A removable processor enclosure apparatus for use in a gaming machine having a housing defining an interior portion, and a first electrical connector disposed in...
US-7,117,396 Scalable CPU error recorder
A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The...
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