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Searching: cpu processor





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Patent # Description
US-RE38,610 Host CPU independent video processing unit
The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed,...
US-6,799,155 Replacement of externally mounted user interface modules with software emulation of user interface module...
The present invention is a method and apparatus for implementing in embedded software the functionality of one or more external user interface circuits either in...
US-6,798,754 Acoustic echo cancellation equipped with howling suppressor and double-talk detector
An acoustic echo canceller (AEC) is devised and tested in a real environment. The devised AEC puts together a number of available digital signal processing...
US-6,792,553 CPU power sequence for large multiprocessor systems
A computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The...
US-6,792,550 Method and apparatus for providing continued operation of a multiprocessor computer system after detecting...
A multiprocessor computer system continues operation after the failure of a cooling device coupled to a central processing unit (CPU). In accordance with the...
US-6,789,097 Real-time method for bit-reversal of large size arrays
A digital signal processor DSP for bit-reversal of a large data array of a size has a direct memory access (DMA) controller for performing in-place bit reversal...
US-6,785,145 Cooling duct for computer
A duct, for channeling air from outside of a personal computer (PC) to cool a processor (CPU) of the PC, has a hollow body. This body comprises spaced apart...
US-6,774,767 Visual messaging system for high-speed networks
The present invention provides a visual messaging device for use with a high speed network. The message data is communicated to the network by a remote device,...
US-6,772,327 Floating point unit pipeline synchronized with processor pipeline
An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the...
US-6,765,931 Gateway with voice
In one aspect of the present invention, a network gateway is configured to facilitate on line and off line bi-directional communication between a number of near...
US-6,763,478 Variable clock cycle for processor, bus and components for power management in an information handling system
A computer system that is able to switch processor and bus frequencies, along with processor voltage, when the system is placed into AC from battery power mode,...
US-6,760,833 Split embedded DRAM processor
A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural...
US-6,757,762 Multi-mode processor bus bridge
A processor bus bridge includes a buffer space disposed between a first bus and a second bus. The first bus is operated in a first mode by a first processor and...
US-6,754,724 Kernel creator for creating kernel capable of executing entertainment processing using a peripheral device
An entertainment apparatus includes a storage unit that stores outside a kernel a device driver for a peripheral device. To make the peripheral device operable,...
US-6,754,241 Computer system for statistical multiplexing of bitstreams
A PC-type computer has a system bus (e.g., a PCI bus) configured with a main CPU board, a statistical multiplexing (stat-mux) board, and a plurality of...
US-6,748,526 CPU stepping and processor firmware matching mechanism
A method and an apparatus for validating a processor firmware ("PF") are disclosed. In one embodiment, at least one version of Processor Firmware ("PF") is...
US-6,748,447 Method and apparatus for scalable distribution of information in a distributed network
The present invention provides a system and apparatus for efficient and reliable, control and distribution of data files or portions of files, applications, or...
US-6,745,487 Downhole cable length measuring apparatus
A wireline cable length measuring apparatus tracks the length and other parameters of a wireline cable in a well bore. The apparatus has three major components:...
US-6,745,335 Power consumption control of multiprocessor system using separate timers for monitoring processor load rise and...
In a multiprocessor system having two CPUs 11-1 and 11-2, processor load monitoring units 12-1 and 12-2 are monitoring the loads on the respective CPUs, and each...
US-6,745,323 Global history vector recovery circuits and methods and systems using the same
A system and method for recovering a global history vector is implemented. In deeply pipelined central processing unit (CPU) architecture instruction fetches may...
US-6,745,296 System and method for providing cacheable smram
Computer systems and methods that provide for cacheable above one megabyte system management random access memory (SMRAM). The systems and methods comprise a...
US-6,745,290 High-speed processor system and cache memories with processing capabilities
The invention is aimed at providing a high-speed processor system capable of performing distributed concurrent processing without requiring modification of...
US-6,744,670 Non-volatile semiconductor memory device
The number of times of rewriting of memory cells is stored by number of rewrite (EW) times storage section. In data rewriting to memory cells, number of...
US-6,738,853 Integrated circuit with built-in processor and internal bus observing method
An LSI with built-in CPU includes a CPU core, an internal CPU bus connected to the CPU core, an external memory access-use external pin for accessing an external...
US-6,738,378 Method and apparatus for intelligent sorting and process determination of data packets destined to a central...
In a network node having one or more packet processors and at least one CPU required to process specific types of packets, a system for managing the specific...
US-6,735,659 Method and apparatus for serial communication with a co-processor
A method and apparatus for serial communication with a co-processor. In one embodiment, a microprocessor is provided with a CPU core, set of serial interface...
US-6,731,657 Multiformat transport stream demultiplexor
The preferred embodiment of the present invention provides an improved receiver that can receive and process many different data types in addition to decoding...
US-6,728,962 Context swapping in multitasking kernel
Disclosed is context swapping in a multitasking operating system for a processor that includes providing a plurality of context blocks for storing context...
US-6,725,396 Identifying field replaceable units responsible for faults detected with processor timeouts utilizing IPL boot...
Described is a method for isolating faults to a correct field replaceable unit (FRU) of a data processing system. When a processor timeout occurs, a fault...
US-6,721,903 Apparatus and method for processing information continuously even against extraneously incoming noise
An inventive information processor performs a predetermined process substantially continuously without causing runaway in its CPU even if extraneous noise has...
US-6,721,848 Method and mechanism to use a cache to translate from a virtual bus to a physical bus
Intermediary inclusive caches (IICs) translate between some number of processors using virtual addressing and a physically addressed bus. The IICs support at...
US-6,718,545 Apparatus for managing resources of a signal processor, a resource managing program transferring method and...
A signal processor executes a required process based on a program stored in a RAM connected to the signal processor. The program is transferred from a ROM...
US-6,718,441 Method to prefetch data from system memory using a bus interface unit
A method and system to prefetch data from system memory to a central processing unit (CPU). The system includes a dynamic random access memory (DRAM) connected...
US-6,717,583 Data processor having unified memory architecture providing priority memory access
In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an...
US-6,714,960 Earnings-based time-share scheduling
A precise earnings-based time-share scheduler schedules multiple jobs in a computer system by apportioning earnings, at scheduler ticks. Earnings are apportioned...
US-6,714,556 In-band management of a stacked group of switches by a single CPU
A switching system includes switches, each having a host processing unit and a switching unit, and a backbone link configured for transferring data packets...
US-6,711,642 Method and chipset for system management mode interrupt of multi-processor supporting system
A method and a chipset for supporting a system management mode interrupt of a multi-processor system. While the central processing is accessing the specified...
US-6,711,526 Operating system-independent method and system of determining CPU utilization
The utilization of a central processing unit during a sampling time interval is determined by measuring a time quantum within the sampling time interval during...
US-RE38,471 Method and apparatus for display image rotation
A method and an apparatus for rotating images on a computer system is disclosed. The system includes a processor for accessing an image frame buffer using a set...
US-6,707,486 Directional motion estimator
An alarm system automatically monitors activity and directional motion in a predetermined area. When the system detects a particular movement in an area, an...
US-6,704,561 Power management system for use with wireless LAN terminal unit
Provided is a power management system for use with a wireless LAN terminal unit, the system having: a CPU having a suspend/resume function, a RAM; a power...
US-6,704,196 Flow-through cooling in-the-round system
A chassis-rack system mounts two 19" RETMA rack chassis back-to-back in the same vertical 1U-space. Each has an independent cooling system that draws-in cold air...
US-6,701,484 Register file with delayed parity check
A register for a computer processor removes the parity check from the critical path of CPU operation, and delays the parity check to the next immediate clock...
US-6,699,128 Manual lever with locking function for mounting CPU enclosure
A removable processor enclosure apparatus for use in a gaming machine having a housing defining an interior portion, and a first electrical connector disposed in...
US-6,691,308 Method and apparatus for changing microcode to be executed in a processor
A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory...
US-6,691,305 Object code compression using different schemes for different instruction types
A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption...
US-6,691,242 SYSTEM TEST AND METHOD FOR CHECKING PROCESSOR OVER-CLOCKING BY RETRIEVING AN ASSIGNED SPEED FROM AN REGISTER...
The present invention is designed to test whether a Central Processing Unit (CPU) in a computer system is being overclocked. That is, being run at a speed higher...
US-6,691,235 Automatic voltage regulation for processors having different voltage requirements and unified or split voltage...
Apparatus for providing electrical power to a processor (CPU) within a computing system includes a fixed-voltage power supply and a programmable power supply....
US-6,691,206 Processor interfacing to memory-centric computing engine
Methods and apparatus are disclosed for interfacing a processor bus or CPU to a computation engine to carry out selected tasks with improved efficiency in the...
US-6,687,903 Inhibiting starvation in a multitasking operating system
Disclosed is inhibiting process starvation in a multitasking operating system by providing a first type of scheduling event at periodic timer intervals,...
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