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Searching: cpu processor





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Patent # Description
US-9,372,734 Outage window scheduler tool
An apparatus for determining a future outage window in which to perform work on a server may include an input for receiving historical performance data about at...
US-9,369,352 Method of capturing server and operating system metrics for virtual to physical topology reporting
A method of improving the accuracy of a topology report, the topology report covering a plurality of operating systems on a plurality of servers, the servers...
US-9,367,494 Data processor and control system
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller...
US-9,367,459 Scheduling method and multi-core processor system
A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when...
US-9,361,259 Integrated circuit with multipurpose processing and for video/audio processing optimization
An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of...
US-9,361,101 Extension of CPU context-state management for micro-architecture state
A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a...
US-9,354,944 Mapping processing logic having data-parallel threads across processors
A method for executing a plurality of data-parallel threads of a processing logic on a processor core includes grouping the plurality of data-parallel threads...
US-9,350,828 Network interface device having general-purpose computing capability
Techniques for a network interface controller (NIC) capable of performing general-purpose computing tasks without intervention from a central processing unit...
US-9,348,657 Method and system of synchronizing processors to the same computational point
A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first...
US-9,342,474 Switching a computer system from a high performance mode to a low power mode
A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a...
US-9,342,384 Function callback mechanism between a central processing unit (CPU) and an auxiliary processor
Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor...
US-9,342,362 Service-processor-centric computer architecture and method of operation thereof
A computer system and a method of operating a service-processor-centric computer system. In one embodiment, the computer system includes: (1) a CPU configured...
US-9,342,350 System for selecting a task to be executed according to an output from a task control circuit
The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided...
US-9,336,557 Apparatus and methods for processing of media signals
Methods and apparatus for processing media signals. In one embodiment, a data processing device processes fixed and variable rate data using a first and second...
US-9,335,982 Processor emulation using multiple translations
Examples described herein emulate a processing architecture using multiple translations of the same source binary. A first translation binary includes compiler...
US-9,323,314 System and method for reducing energy usage in a mobile communications device
A mobile communications device and a method for reducing energy usage in a mobile communications device are provided. An example mobile communications device...
US-9,323,307 Active display processor sleep state
Power consumption and dissipation is reduced during active display of content from an internal display buffer using a power supply topology that powers a...
US-9,317,090 Methods and apparatuses for operating a data processing system
Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system...
US-9,310,863 Multi-purpose power controller and method
The present invention provides a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size...
US-9,307,054 Intelligent network interface system and method for accelerated protocol processing
A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with...
US-9,304,834 Parallel runtime execution on multiple processors
A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or...
US-9,304,806 Provisioning virtual CPUs using a hardware multithreading parameter in hosts with split core processors
A cloud manager monitors available resources on host computer systems, including a number of hardware threads supported by CPUs on the host computer systems and...
US-9,304,805 Provisioning virtual CPUs using a hardware multithreading parameter in hosts with split core processors
A cloud manager monitors available resources on host computer systems, including a number of hardware threads supported by CPUs on the host computer systems and...
US-9,304,794 Virtual machine control method and virtual machine system using prefetch information
Provided is a virtual machine including a first virtualization module operating on a physical CPU, for providing a first CPU, and a second virtualization module...
US-9,298,768 System and method for the parallel execution of database queries over CPUs and multi core processors
The invention relates to a system for parallel execution of database queries over one or more Central Processing Units (CPUs), and one or more Multi Core...
US-9,295,910 Methods, apparatus and systems for use of a non-native chipset to play original video game cartridges
Apparatus, methods and systems using a more powerful, but non-native, modern CPU/GPU chipset to play one or more types of original console games. The apparatus,...
US-9,292,342 Schedule based execution with extensible continuation based actions
Generally in a computing environment, executing work based on time (i.e. according to a predetermined schedule) is a common need. However, in cloud based...
US-9,288,334 Modem with voice processing capability
A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far...
US-9,286,216 3DIC memory chips including computational logic-in-memory for performing accelerated data processing
This disclosure relates to a three-dimensional (3D) integrated circuit (3DIC) memory chip including computational logic-in-memory (LiM) for performing...
US-9,280,473 Method and apparatus for accessing physical memory from a CPU or processing element in a high performance manner
A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor...
US-9,275,733 Methods and systems for mapping a peripheral function onto a legacy memory interface
A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and...
US-9,270,697 Hardware-assisted integrity monitor
A hardware-assisted integrity monitor may include one or more target machines and/or monitor machines. A target machine may include one or more processors,...
US-9,268,389 Reducing power consumption on a processor system by masking actual processor load with insertion of dummy...
Energy savings can be obtained by masking a computationally-intensive task from a processor performance management system which selects the processor...
US-9,264,509 Direct cache access for network input/output devices
Methods and systems for improving efficiency of direct cache access (DCA) are provided. According to one embodiment, a DCA control is defined by a network...
US-9,264,366 Method and apparatus for processing received network packets on a network interface for a computer
An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a...
US-9,262,166 Efficient implementation of RSA using GPU/CPU architecture
Various embodiments are directed to a heterogeneous processor architecture comprised of a CPU and a GPU on the same processor die. The heterogeneous processor...
US-9,252,752 Clock generation circuit, processor system using same, and clock frequency control method
A microcomputer includes a register that stores division ratio setting information, a frequency divider that determines first and second division ratios based...
US-9,244,826 Managing CPU resources for high availability micro-partitions
Profile properties in a partition profile are user-configurable through a management entity such as a management console. A partition manager calculates a...
US-9,244,825 Managing CPU resources for high availability micro-partitions
Profile properties in a partition profile are user-configurable through a management entity such as a management console. A partition manager calculates a...
US-9,244,739 Applications processing in a network apparatus
A method and system for distributing flows between a multiple processors. The flows can be received from an external source such as a network, by a front-end...
US-9,244,732 Compensating threads for microarchitectural resource contentions by prioritizing scheduling and execution
A thread (or other resource consumer) is compensated for contention for system resources in a computer system having at least one processor core, a last level...
US-9,244,648 Multi-processor video processing system and video image synchronous transmission and display method therein
The present invention relates to the field of video processing. Disclosed are a multi-processor video processing system and video image synchronous transmission...
US-9,235,871 Method and system of a command buffer between a CPU and GPU
A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes...
US-9,232,139 Image stabilization using striped output transformation unit
An image signal processor of a device, apparatus, or computing system that includes a camera capable of capturing video clips may be configured to apply...
US-9,230,091 Managing use of a field programmable gate array with isolated components
Field programmable gate arrays can be used as a shared programmable co-processor resource in a general purpose computing system. Components of an FPGA are...
US-9,229,756 User datagram protocol (UDP) packet migration in a virtual machine (VM) migration
Embodiments of the invention relate to receiving, by a first processor comprising a processing device, an indication that a migration of a virtual machine from...
US-9,229,755 User datagram protocol (UDP) packet migration in a virtual machine (VM) migration
Embodiments of the invention relate to receiving, by a first processor comprising a processing device, an indication that a migration of a virtual machine from...
US-9,219,832 Portable handheld device with multi-core image processor
A portable handheld device includes an image sensor for capturing an image; and a one-chip microcontroller having integrated therein a CPU for processing a...
US-9,207,939 Performing shadowing function by virtual machine manager in two-level virtual machine environment
There is a need for providing the Xeon CPU with a two-level VM that is independent of VMM types and prevents the throughput from degrading when the OS operates...
US-9,207,661 Dual core architecture of a control module of an engine
A control system for a control module of a vehicle includes a first integrated circuit (IC) core of a primary processor that generates a first control signal...
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