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Searching: cpu processor





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Patent # Description
US-6,735,659 Method and apparatus for serial communication with a co-processor
A method and apparatus for serial communication with a co-processor. In one embodiment, a microprocessor is provided with a CPU core, set of serial interface...
US-6,731,657 Multiformat transport stream demultiplexor
The preferred embodiment of the present invention provides an improved receiver that can receive and process many different data types in addition to decoding...
US-6,728,962 Context swapping in multitasking kernel
Disclosed is context swapping in a multitasking operating system for a processor that includes providing a plurality of context blocks for storing context...
US-6,725,396 Identifying field replaceable units responsible for faults detected with processor timeouts utilizing IPL boot...
Described is a method for isolating faults to a correct field replaceable unit (FRU) of a data processing system. When a processor timeout occurs, a fault...
US-6,721,903 Apparatus and method for processing information continuously even against extraneously incoming noise
An inventive information processor performs a predetermined process substantially continuously without causing runaway in its CPU even if extraneous noise has...
US-6,721,848 Method and mechanism to use a cache to translate from a virtual bus to a physical bus
Intermediary inclusive caches (IICs) translate between some number of processors using virtual addressing and a physically addressed bus. The IICs support at...
US-6,718,545 Apparatus for managing resources of a signal processor, a resource managing program transferring method and...
A signal processor executes a required process based on a program stored in a RAM connected to the signal processor. The program is transferred from a ROM...
US-6,718,441 Method to prefetch data from system memory using a bus interface unit
A method and system to prefetch data from system memory to a central processing unit (CPU). The system includes a dynamic random access memory (DRAM) connected...
US-6,717,583 Data processor having unified memory architecture providing priority memory access
In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an...
US-6,714,960 Earnings-based time-share scheduling
A precise earnings-based time-share scheduler schedules multiple jobs in a computer system by apportioning earnings, at scheduler ticks. Earnings are apportioned...
US-6,714,556 In-band management of a stacked group of switches by a single CPU
A switching system includes switches, each having a host processing unit and a switching unit, and a backbone link configured for transferring data packets...
US-6,711,642 Method and chipset for system management mode interrupt of multi-processor supporting system
A method and a chipset for supporting a system management mode interrupt of a multi-processor system. While the central processing is accessing the specified...
US-6,711,526 Operating system-independent method and system of determining CPU utilization
The utilization of a central processing unit during a sampling time interval is determined by measuring a time quantum within the sampling time interval during...
US-RE38,471 Method and apparatus for display image rotation
A method and an apparatus for rotating images on a computer system is disclosed. The system includes a processor for accessing an image frame buffer using a set...
US-6,707,486 Directional motion estimator
An alarm system automatically monitors activity and directional motion in a predetermined area. When the system detects a particular movement in an area, an...
US-6,704,561 Power management system for use with wireless LAN terminal unit
Provided is a power management system for use with a wireless LAN terminal unit, the system having: a CPU having a suspend/resume function, a RAM; a power...
US-6,704,196 Flow-through cooling in-the-round system
A chassis-rack system mounts two 19" RETMA rack chassis back-to-back in the same vertical 1U-space. Each has an independent cooling system that draws-in cold air...
US-6,701,484 Register file with delayed parity check
A register for a computer processor removes the parity check from the critical path of CPU operation, and delays the parity check to the next immediate clock...
US-6,699,128 Manual lever with locking function for mounting CPU enclosure
A removable processor enclosure apparatus for use in a gaming machine having a housing defining an interior portion, and a first electrical connector disposed in...
US-6,691,308 Method and apparatus for changing microcode to be executed in a processor
A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory...
US-6,691,305 Object code compression using different schemes for different instruction types
A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption...
US-6,691,242 SYSTEM TEST AND METHOD FOR CHECKING PROCESSOR OVER-CLOCKING BY RETRIEVING AN ASSIGNED SPEED FROM AN REGISTER...
The present invention is designed to test whether a Central Processing Unit (CPU) in a computer system is being overclocked. That is, being run at a speed higher...
US-6,691,235 Automatic voltage regulation for processors having different voltage requirements and unified or split voltage...
Apparatus for providing electrical power to a processor (CPU) within a computing system includes a fixed-voltage power supply and a programmable power supply....
US-6,691,206 Processor interfacing to memory-centric computing engine
Methods and apparatus are disclosed for interfacing a processor bus or CPU to a computation engine to carry out selected tasks with improved efficiency in the...
US-6,687,903 Inhibiting starvation in a multitasking operating system
Disclosed is inhibiting process starvation in a multitasking operating system by providing a first type of scheduling event at periodic timer intervals,...
US-6,687,851 Method and system for upgrading fault-tolerant systems
The inventive system includes an I/O subsystem that controls the synchronization of an off-line CPU to an on-line CPU, such that much of the synchronization...
US-6,687,811 Processor with trace memory for storing access information on internal bus
An internal trace memory is provided in a processor, the internal trace memory, in the trace mode, storing internal bus access information and in the normal...
US-6,687,344 Parallel handset on-hook/off-hook detection by software-based signal power measurement
A computer having a modem is programmed with software (also called a "on-hook/off-hook detector") that detects a change in status (e.g., on-hook or off-hook) of...
US-6,680,604 Methods to control the droop when powering dual mode processors and associated circuits
A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The...
US-6,678,801 DSP with distributed RAM structure
A multi-processor system includes a global bus (14) having associated therewith a global address space with a plurality of processor nodes (10) associated...
US-6,678,765 Embedded modem
An embedded system that has a general purpose central processing unit CPU and a digital signal processor DSP, the CPU is adapted to perform various tasks such as...
US-6,678,176 Method and apparatus for a solar power conditioner
A method and apparatus for supplementing electrical power production during peak demand power consumption is presented. A solar power conditioner converts DC...
US-6,677,983 Electronic endoscope
An electronic endoscope includes a processor by which an image captured by an endoscope is displayed on a screen of a monitor. Panel switches, a central...
US-6,677,951 Entertainment apparatus having compatibility and computer system
An entertainment apparatus is configured to enable a program for an older version of the apparatus to be executed. In a normal mode, a main processing unit (MPU)...
US-6,674,536 Multi-instruction stream processor
The present invention discloses apparatus for, and a method of, rendering image data prior to outputting of the resulting image. A graphics co-processor (224) is...
US-6,669,566 Video game apparatus and method for uniquely enabling play of multiple games
In a game processor GP that enable a player to play a plurality of games interrelated to each other, flash memory 12 stores a plurality of game programs PG...
US-6,658,602 Apparatus for detecting abnormal execution of program
An apparatus for detecting abnormality in execution state of a control program. An electronic control unit to which the apparatus for detecting abnormality is...
US-6,658,448 System and method for assigning processes to specific CPU's to increase scalability and performance of...
A method in a multi-processor computing system is disclosed. The method is an object-oriented method that allows a user to make associations between processes to...
US-6,651,250 Digital broadcast receiving system in information processor
A digital satellite broadcast receiving system is proposed in which the necessary packets of an MPEG2-based transport stream can be transferred to the system...
US-6,651,126 Snapshot arbiter mechanism
A snapshot arbiter system for servicing multiple interrupt requests for a central processing unit (CPU) in a digital processor system, and for providing...
US-6,647,486 Information processing apparatus for entertainment system utilizing DMA-controlled high-speed transfer and...
Routine processing for routine data, non-routine processing for routine data and general non-routine processing are to be processed efficiently. To this end, a...
US-6,647,475 Processor capable of enabling/disabling memory access
A low-end microprocessor 10 includes a stack pointer 18 storing a word SPV, a comparator 17 comparing the SPV with a given value ADR1, an inverter 19 inverting...
US-6,647,465 Realtime parallel processor system for transferring common information among parallel processors to a cache...
A CPU system having a built-in cache memory system in which a write-only port for coherence control from the common system side and an access port from the CPU...
US-6,643,720 Data transfer control method, and peripheral circuit, data processor and data processing system for the method
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a...
US-6,643,680 Signal processing system which can reduce burden applied to a CPU or a signal processor
In a signal processing system, a plurality of mutually different applications are simultaneously executed. In the system, combinations of applications are...
US-6,640,195 Integrated services hub self speed detection
The present invention discloses a method of automatically detecting and storing the CPU clock frequency in a telecommunications hub. The hub includes a known...
US-6,639,810 Inverter apparatus for controlling a generator output to sign-wave voltage
An inverter 3 is controlled by feeding back an output voltage waveform for stabilizing the output and circuitry simplification. The output waveform of an...
US-6,636,980 System for launching data on a bus by using first clock for alternately selecting data from two data streams...
A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is...
US-6,636,907 Transferring data between asynchronous devices
A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are...
US-6,633,916 Method and apparatus for virtual resource handling in a multi-processor computer system
Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected...
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