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Searching: cpu processor





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Patent # Description
US-6,651,126 Snapshot arbiter mechanism
A snapshot arbiter system for servicing multiple interrupt requests for a central processing unit (CPU) in a digital processor system, and for providing...
US-6,647,486 Information processing apparatus for entertainment system utilizing DMA-controlled high-speed transfer and...
Routine processing for routine data, non-routine processing for routine data and general non-routine processing are to be processed efficiently. To this end, a...
US-6,647,475 Processor capable of enabling/disabling memory access
A low-end microprocessor 10 includes a stack pointer 18 storing a word SPV, a comparator 17 comparing the SPV with a given value ADR1, an inverter 19 inverting...
US-6,647,465 Realtime parallel processor system for transferring common information among parallel processors to a cache...
A CPU system having a built-in cache memory system in which a write-only port for coherence control from the common system side and an access port from the CPU...
US-6,643,720 Data transfer control method, and peripheral circuit, data processor and data processing system for the method
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a...
US-6,643,680 Signal processing system which can reduce burden applied to a CPU or a signal processor
In a signal processing system, a plurality of mutually different applications are simultaneously executed. In the system, combinations of applications are...
US-6,640,195 Integrated services hub self speed detection
The present invention discloses a method of automatically detecting and storing the CPU clock frequency in a telecommunications hub. The hub includes a known...
US-6,639,810 Inverter apparatus for controlling a generator output to sign-wave voltage
An inverter 3 is controlled by feeding back an output voltage waveform for stabilizing the output and circuitry simplification. The output waveform of an...
US-6,636,980 System for launching data on a bus by using first clock for alternately selecting data from two data streams...
A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is...
US-6,636,907 Transferring data between asynchronous devices
A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are...
US-6,633,916 Method and apparatus for virtual resource handling in a multi-processor computer system
Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected...
US-6,631,422 Network adapter utilizing a hashing function for distributing packets to multiple processors for parallel...
Network input processing is distributed to multiple CPUs on multiprocessor systems to improve network throughput and take advantage of MP scalability. Packets...
US-6,625,759 Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit
A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are...
US-6,601,134 Multi-processor type storage control apparatus for performing access control through selector
A storage control apparatus is coupled to a central processing unit (CPU) and a storage unit to control input/output of data between the CPU and the storage...
US-6,598,099 Data transfer control method, and peripheral circuit, data processor and data processing system for the method
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a...
US-6,594,778 Duplexing structure of switching system processor and method for maintaining memory coherency
A duplexing structure of a switching system processor and a method for maintaining a memory coherency are provided in which both data of an active memory and of...
US-6,593,727 Data processor and data processing method for wavemeter
The CPU outputs to the delay circuit 22 delay time setting signals for setting the delay time, based on input delay time data input from an external input...
US-6,591,284 Method for performing a fast transform
The power consumption, memory allocation, and CPU time used in a signal processor executing a fast transform can be optimized by using a particular method of...
US-6,587,938 Method, system and program products for managing central processing unit resources of a computing environment
Central processing unit (CPU) resources are managed within a computing environment. When the allocation of CPU resources to a partition of the computing...
US-6,587,635 Subpicture master control
A method for operating a digital video processor including a CPU and a memory to control the presentation of demultiplexed subpicture unit ("SPU") data. The play...
US-6,584,538 Information processing system
An information processing system is configured such that which when an application handling multimedia, especially, moving images is performed by an information...
US-6,584,085 Apparatus for and method of allocating D-channel to minimum channel when performing basic rate interface...
An apparatus for and a method of allocating D-channel to minimum channel when performing a basic rate interface (BRI) in WLL, in which D-channel is allocated to...
US-6,578,110 High-speed processor system and cache memories with processing capabilities
The invention is aimed at providing a high-speed processor system capable of performing distributed concurrent processing without requiring modification of...
US-6,577,640 Format programmable hardware packetizer
A format programmable hardware packetizer (110) receives real-time raw input data (125) from a multimedia data source (103) via an analog to digital converter...
US-6,574,739 Dynamic power saving by monitoring CPU utilization
A CPU activity monitoring circuit is electrically connected to a CPU. This circuit monitors the state of a bus signal line on the CPU, as there is a strong...
US-6,574,738 Method and apparatus to control processor power and performance for single phase lock loop (PLL) processor systems
An integrated circuit contains a central processing unit ("CPU"), a graphic control hub ("GCH"), a memory control hub ("MCH"), and a phase lock loop ("PLL"). The...
US-6,567,963 Wafer scale integration and remoted subsystems using opto-electronic transceivers
An apparatus and method for optically interconnecting subsystems of a microprocessor system, whether co-located on a common wafer or divided among two or more...
US-6,564,334 Programmable output generator
A memory mapped programmable output generator, capable of producing events such as creating complex waveforms, triggering analog to digital and digital to analog...
US-6,563,863 Computer modem
A service chip for use with a computer. The chip includes a CPU interface, a transceiver interface, an adaptive echo cancellation filter, a monitor, and first...
US-6,560,754 Method and apparatus for jump control in a pipelined processor
An improved method and apparatus for controlling and implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor....
US-6,557,065 CPU expandability bus
Embodiments of the present invention provide a computer system with a high speed, high bandwidth expandability bus for integrated and non-integrated CPU...
US-6,553,435 DMA transfer method for a system including a single-chip processor with a processing core and a device...
A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing...
US-6,552,753 Method and apparatus for maintaining uniform sound volume for televisions and other systems
Apparatus for maintaining uniform volume in television or audio system forms part of television set and contains an eight-bit DSP having a CPU, RAM and ROM...
US-6,546,449 Video controller for accessing data in a system and method thereof
A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics...
US-6,542,983 Microcomputer/floating point processor interface and method
In a computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU execution pipeline...
US-6,542,950 Self-adaptive processor overload control system
The self-adaptive processor overload control system provides real time overload control and is fast to respond to processing overload conditions. The...
US-6,539,500 System and method for tracing
The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly...
US-6,535,942 Method for reducing processor interrupt load
A method for reducing interrupt load in a multi-processor system is disclosed, whereby two central processors executing a real-time operating system can...
US-6,532,019 Input/output integrated circuit hub incorporating a RAMDAC
A computer system includes a first integrated circuit that has a central processing unit (CPU) and a graphics controller. An I/O hub, which is coupled to a...
US-6,529,981 Bus arbiter
A bus arbiter capable of avoiding needless increase in circuit scale is provided. The bus arbiter controls a bus shared by a CPU (central processing unit) and a...
US-6,529,930 Methods and apparatus for performing a signed saturation operation
Methods and apparatus for performing signed saturation of binary numbers to arbitrary powers of two are described. Given an n-bit signed binary word, the methods...
US-6,526,163 Ultrasound system with parallel processing architecture
An ultrasound system operating on a personal computer architecture comprising multiple processors controlled to operate in parallel to share ultrasound...
US-6,525,985 Semiconductor memory device
A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are...
US-6,525,690 Golf course yardage and information system with zone detection
A player position determining and course management system for a golf course having a plurality of roving units for use by players in playing the course is...
US-6,523,136 Semiconductor integrated circuit device with processor
A multiplexer is provided for selecting Central Processing Unit (CPU) operation trace information sent from a debug support unit and an internal signal on an...
US-6,523,095 Method and data processing system for using quick decode instructions
A cache line of a cache (230) contains a modifiable instruction. The modifiable instruction is decoded by a central processor unit (210) (CPU) which performs the...
US-6,513,124 Method and apparatus for controlling operating speed of processor in computer
The number of executed instructions (I.sub.u) in a user mode as one of performance indexes of a computer, and the total number of executed instructions (I.sub.t)...
US-6,513,102 Internal copy for a storage controller
A storage system has a storage controller connected to a plurality of storage devices. The described system and method transfer physical data from a first...
US-6,502,182 Digital signal processing device
A digital signal processing device applicable to a signal processing system using a CPU is mainly configured by an external memory and a digital signal processor...
US-6,499,059 Method of controlling a network element using a service profile and apparatus of the same
A network element (NE) for a communications network, particularly for a synchronous digital communications system, is disclosed. It comprises a controller (CT)...
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