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Searching: cpu processor





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Patent # Description
US-6,333,745 Data processor having unified memory architecture providing priority memory access
In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an...
US-6,332,215 Java virtual machine hardware for RISC and CISC processors
A hardware Java accelerator is provided to implement portions of the Java virtual machine in hardware in order to accelerate the operation of the system on Java...
US-6,331,935 Controller assembly having a base unit with a dockable processor unit
A controller assembly utilizes a base unit that receives a dockable processor unit. The controller assembly typically is a programmable logic controller that...
US-6,330,745 Method for making a modular integrated apparatus for heat dissipation
A modular integrated apparatus and method that integrates mechanical, electrical, and thermal management, and that includes a computer processor (CPU), or VLSI...
US-6,330,629 Information processing system
An information processing system is configured such that which when an application handling multimedia, especially, moving images is performed by an information...
US-6,330,579 Fir filter based upon squaring
An improved FIR filter based upon squaring is used to self-determine a filter constant equal to the sum-of-squares of the filter coefficients. An input signal is...
US-6,322,444 Video game with displayed bar for indicating target position
A video game system has a controller including a CPU which functions as a controller action detecting unit, a target position calculating unit, and a cursor...
US-6,321,318 User-configurable on-chip program memory system
A processor structure and method of operation are disclosed that comprise a user-configurable on-chip program memory system. The memory system comprises an...
US-6,321,307 Computer system and method employing speculative snooping for optimizing performance
A computer system includes a bus bridge which provides an interface between a processor bus, a main memory and a peripheral bus such as a PCI or AGP bus. When a...
US-6,321,279 System for implementing intelligent I/O processing in a multi-processor system by redirecting I/O messages to a...
A software program is used in conjunction with a standard general purpose multi-processor computer system as a means of implementing an I.sub.2 O-compliant...
US-6,319,198 Electronic endoscope
In an electronic endoscope, a video-scope has an image sensor for photographing an object image and a light guide for guiding light toward an object. A...
US-6,311,289 Explicit state copy in a fault tolerant system using a remote write operation
The present invention provides a new method for performing re-integration of a CPU in a fault tolerant computer system. One of a "remote write" operation and a...
US-6,311,204 Processing system with register-based process sharing
A method and apparatus for preventing interference between simultaneously-running processes in a set top box processing system which attempt to access certain...
US-6,311,149 Reconfigurable test system
A reconfigurable test system including a host computer coupled to a reconfigurable test instrument. The reconfigurable test instrument includes reconfigurable...
US-6,310,779 System for attaching cartridge-type CPU to a board
The system provided attaches a cartridge-type central processor unit (CPU) to a motherboard and includes a first device, a second device and a third device. The...
US-6,308,256 Secure execution of program instructions provided by network interactions with processor
A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that...
US-6,308,234 Flexible processing hardware architecture
A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a...
US-6,304,981 Adaptive shutdown system and method for an information handling system
A system for effecting a shutdown of a networked information handling system automatically determines the time interval required for the information handling...
US-6,304,656 Power supplying to CPU of telephone
An automatic power supplying device for providing power for a CPU of a telephone to activate the CPU and wake up a downstream circuit including for example a...
US-6,298,438 System and method for conditional moving an operand from a source register to destination register
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-6,298,392 Concurrent programming apparatus with status detection capability
A computer controlled group of programmer sites are provided to burn in or enter operating code into various types of programmable electronic devices, such as...
US-6,297,814 Apparatus for and method of displaying image and computer-readable recording medium
A control system of a game apparatus, such as a racing game apparatus, has a CPU for controlling a signal processor based on a program stored in a ...
US-6,295,574 Real time interrupt handling for superscalar processors
A CPU includes a real time interrupt (RTI) control unit configured to control real time interrupt capabilities of the CPU. Upon receipt of a real time interrupt...
US-6,294,982 Visual messaging system for high speed networks
The present invention provides a visual messaging device for use with a high speed network. The message data is communicated to the network by a remote device,...
US-6,292,814 Methods and apparatus for implementing a sign function
Methods and apparatus for implementing and using a sign(x) function are described. In accordance with the present invention, the sign(x) function is implemented...
US-6,292,705 Method and apparatus for address transfers, system serialization, and centralized cache and transaction...
A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses...
US-6,289,473 Semiconductor device having a debug function
Provided is a semiconductor device capable of dealing with various debug patterns, of knowing whether or not an operation of each module is stopped when...
US-6,289,376 Tightly-coupled disk-to-CPU storage server
A storage server for efficiently retrieving data from a plurality of disks in response to user access requests. The server comprises a plurality of processors...
US-6,288,993 Computer-controlled game device with cassette ROM and CD-ROM
A processing device is provided with a disk loading port and a cassette or cartridge loading port both formed in a substantially common top face or surface of...
US-6,285,407 Multi-function TV receiver
A multi-function TV receiver capable of performing the processing related to an object transmitted through the broadcasting and an object which is derived from...
US-6,279,087 System and method for maintaining coherency and improving performance in a bus bridge supporting write posting...
A bridge logic unit provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to memory bus, and a peripheral device...
US-6,275,893 Method and apparatus for providing seamless hooking and intercepting of selected kernel and HAL exported entry...
In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes...
US-6,275,885 System and method for maintaining ownership of a processor bus while sending a programmed number of snoop...
A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus...
US-6,275,491 Programmable architecture fast packet switch
A programmable fast packet switch testbed (10) for use in the evaluation of prototype architectures and traffic management algorithms is disclosed. The...
US-6,272,651 System and method for improving processor read latency in a system employing error checking and correction
A computer is provided having a system interface unit coupled between main memory, a CPU bus, and a PCI bus and/or graphics bus. A hard drive is typically...
US-6,269,443 Method and apparatus for automatically selecting CPU clock frequency multiplier
An apparatus for automatically selecting a processor clock frequency multiplier is disclosed. The apparatus includes a reset circuit that transmits a reset...
US-6,269,379 Medical image filing system enabling registration and retrieval of a plurality of medical images
In an image filing system in accordance with the present invention, image files containing images that should be displayed on a viewing monitor in a conference...
US-6,266,696 Full time network auxiliary for a network connected PC
A client on a network is provided with auxiliary low power logic, at the network adaptor, that is always active and simulates network traffic (e.g. Ethernet...
US-6,266,242 Circuit module and information processing apparatus
The present invention provides an information processing apparatus that may be designed in small and thin size and a small and thin CPU module that has a high...
US-6,263,452 Fault-tolerant computer system with online recovery and reintegration of redundant components
A computer system in a fault-tolerant configuration employees multiple identical CPUs executing the same instruction stream, with multiple, identical memory...
US-6,263,073 Method of improving the CAS tone signal detection of a telephone and the apparatus therefor
A method of improving the CAS (customer premises equipment alert signal) tone signal detection of a telephone which uses a CAS tone signal detection chip or data...
US-6,253,290 Multiprocessor system capable of circumventing write monitoring of cache memories
A multiprocessor system having a plurality of processor units each including a CPU and a local cache memory connected to the CPU. The CPUs have their shared bus...
US-6,253,152 Navigation controller
A navigation controller includes, in addition to a main CPU in the form of a general purpose CPU, a media processor having a VLIW structure or an SIMD structure....
US-6,249,812 Interactive system support using a system management asic
A client on a network is provided with auxiliary low power logic, at the network adaptor, that is always active and simulates network traffic (e.g., Ethernet...
US-6,247,109 Dynamically assigning CPUs to different partitions each having an operation system instance in a shared memory...
Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected...
US-6,247,060 Passing a communication control block from host to a local device such that a message is processed on the device
A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with...
US-6,246,418 Data processing method and apparatus
In a data processing system for improving processing speed, a main CPU transmits coordinates of a center point in a three-dimensional space over a main bus 101...
US-6,243,823 Method and system for boot-time deconfiguration of a memory in a processing system
A method and system for deconfiguring software in a processing system is disclosed. In one aspect, a processing system comprises a central processing unit (CPU),...
US-6,243,791 Method and architecture for data coherency in set-associative caches including heterogeneous cache sets having...
A processor architecture and method are shown which involve a cache having heterogeneous cache sets. An address value of a data access request from a CPU is...
US-6,243,123 Light beam scanning apparatus for use with image forming apparatus
In a digital copying machine using a multi-beam optical system, a light beam position detector situated on a line extended from the surface of a photosensitive...
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