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Searching: cpu processor
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| Patent # | Description |
|---|---|
| US-6,158,656 |
Final accommodation device for power-source drop A method and apparatus for enabling a processor to execute processing routine even if a power-source voltage drop occurs during processing. When an ignition key... |
| US-6,158,023 |
Debug apparatus The present invention provides a debug apparatus that can set complex break conditions, minimize a time lag from the detection of a break event to the break an... |
| US-6,158,020 |
Remote jumper set and reset A client on a network is provided with auxiliary low power logic, at the network adapter, that is always active and simulates network traffic (e.g. Ethernet... |
| US-6,157,984 |
Integrated controller/processor for disc drive having direct memory
access A single chip integrated disc/servo controller and processor (CPU) for a disc drive reduces timing overhead associated with processor/controller/memory... |
| US-6,157,967 |
Method of data communication flow control in a data processing system
using busy/ready commands A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit... |
| US-6,157,397 |
AGP read and CPU wire coherency A method for graphics device read and processor write coherency receives a write request from a processor to write data to a storage element for a component to... |
| US-6,154,831 |
Decoding operands for multimedia applications instruction coded with
less number of bits than combination of... A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a... |
| US-6,154,830 |
Microprocessor On a microprocessor chip mounting a central processing unit (CPU) for controlling the entire operation of electronic equipment and a digital signal processor... |
| US-6,154,827 |
Data processor capable of high speed accessing A data processor capable of accessing data with the data processing capacity of a central processing unit (CPU), even if the data processing capacity of the CPU... |
| US-6,154,785 |
Inter-processor communication system An inter-processor communication system for a multi-processor environment wherein each processor has an associated processor system controller comprising an... |
| US-6,151,689 |
Detecting and isolating errors occurring in data communication in a
multiple processor system A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit... |
| US-6,147,863 |
Industrial computer An industrial computer including a passive backplane generally compliant with the PCI/ISA industrial standard promulgated by the PICMG technical committee, but... |
| US-6,145,102 |
Transmission of an error message over a network by a computer which
fails a self-test A computer may have a management bus installed, where the management bus is coupled to sensors which monitor status of components of the computer. The management... |
| US-6,145,100 |
Debug interface including timing synchronization logic A system for debugging a processor includes a logic circuit for communicating commands and data between an input/output port which operates at a first clock... |
| US-6,144,460 |
Data processing method, and data processor and printer using data
processing method A data processing method which efficiently performs data transfer by using a data bus with an appropriate access width corresponding to transfer data and a... |
| US-6,144,322 |
Variable length code processor with encoding and/or decoding A variable length code processor is obtained which can perform encoding or decoding process in a plurality of variable length encoding standards. A sequence... |
| US-6,141,673 |
Microprocessor modified to perform inverse discrete cosine transform
operations on a one-dimensional matrix of... A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a... |
| US-6,141,306 |
Optical disc drive and methods of examining the optical disc drive An optical disc drive for recording and playing back a recordable-type optical disc includes a driving mechanism for rotating the optical disc, an optical... |
| US-6,134,308 |
Caller ID logging: entry storage on a per line basis A telephone system with a caller ID logging feature includes a plurality of telephone stations which share a plurality of telephone lines connected to the... |
| US-6,130,898 |
Simulcasting digital video programs for broadcast and interactive
services To provide interactivity, a public wireless packet data network is combined with a broadband digital broadcast network. In the preferred embodiment, the... |
| US-6,128,763 |
Dynamically changing forward error correction and automatic request for
repetition A transceiver device having a forward error correction decoder providing at least one forward error correction metric and a data integrity monitor providing at... |
| US-6,128,702 |
Integrated processor/memory device with victim data cache An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The... |
| US-6,124,865 |
Duplicate cache tag store for computer graphics system A duplicate cache tag store, accessible to a graphics processor and to devices connected to the I/O bus without creating traffic on the system bus. Any entry... |
| US-6,122,716 |
System and method for authenticating a computer memory A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive... |
| US-6,122,713 |
Dual port shared memory system including semaphores for high priority
and low priority requestors A system and method for controlling access to a dual port shared memory in a system comprising a host computer system and a communication device comprised in or... |
| US-6,122,699 |
Data processing apparatus with bus intervention means for controlling
interconnection of plural busses This invention has as its object to improve the net processing speed by appropriately assigning the DMA processing time for attaining high-speed processing using... |
| US-6,122,696 |
CPU-peripheral bus interface using byte enable signaling to control byte
lane steering A CPU-Peripheral bus interface for 64-bit local bus to 32-bit peripheral bus uses byte enable signaling to provide byte lane steering. Qbuffer logic provides a... |
| US-6,119,219 |
System serialization with early release of individual processor A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex... |
| US-6,115,791 |
Hierarchical cache system flushing scheme based on monitoring and
decoding processor bus cycles for flush/clear... An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU... |
| US-6,115,757 |
DMA control apparatus for multi-byte serial-bit transfer in a
predetermined byte pattern and between memories... A DMA control apparatus transfers a data set of bytes, with no intermixing these data bytes and with favorable efficiency. A DMA controller receives data bytes... |
| US-6,115,036 |
Video game/videographics program editing apparatus with program halt and
data transfer features A videographics/video game fabricating system includes a multiprocessor based game processor console which includes a main central processing unit (CPU) which... |
| US-6,112,303 |
Computer system with system ROM including serial-access PROM coupled to
an auto-configuring memory controller... A computer system having a processor is provided with a memory controller serially coupled to a serial-access programmable ROM (PROM) through the serial PROM... |
| US-6,112,290 |
Communication system signal processing apparatus with ROM stored signal
procedures executed RAM A signal processing apparatus is disclosed which includes a low speed ROM (9) for storing a plurality of signal procedures, a high speed RAM (4) used by a... |
| US-6,112,287 |
Shared memory multiprocessor system using a set of serial links as
processors-memory switch A multiprocessor system comprising a core memory (RAM), processing units (CPU.sub.1 -CPU.sub.j), each being provided with a cache memory (MCj), a directory... |
| US-6,108,792 |
Article for providing continuity of operation in a computer An apparatus for providing continuity of operation in system which performs a process having CPU, input/output, main memory and power supply by restoring the... |
| US-6,108,204 |
CPU heat sink A cooling system for a multi processor system mounted in a rack that has a top, a bottom, sides and a plurality of card cages. Each of the card cages has card... |
| US-6,105,145 |
System and method for generating high resolution clockticks in a
computer system A system and method is provided by the present invention for transmitting or receiving data to or from a computer system by reprogramming the computer system's... |
| US-6,104,417 |
Unified memory computer architecture with dynamic graphics memory
allocation A computer system provides dynamic memory allocation for graphics. The computer system includes a memory controller, a unified system memory, and memory clients... |
| US-6,104,251 |
Method and apparatus for providing transient suppression in a central
processor unit (CPU) phase locked loop... The present invention is directed to apparatus and methods for reducing transient signals in phase locked loop (PLL) circuits of central processing units. One... |
| US-6,101,610 |
Computer system having thermal sensing with dual voltage sources for
sensor stabilization A computer system employs a thermal sensor in the main CPU housing to detect operating temperature. If a preselected trip point is reached indicating that... |
| US-6,101,599 |
System for context switching between processing elements in a pipeline
of processing elements A system and technique facilitate fast context switching among processor complex stages of a pipelined processing engine. Each processor complex comprises a... |
| US-6,097,955 |
Apparatus and method for optimizing CPU usage in processing paging
messages within a cellular communications system An application processor within a distributed network of a cellular communications system minimizes CPU resource consumption for processing paging messages by... |
| US-6,097,356 |
Methods of improving display uniformity of thin CRT displays by
calibrating individual cathode Methods of improving the display uniformity of a thin CRT display are disclosed. These methods can provide nearly perfect display uniformity for a thin CRT... |
| US-6,094,699 |
Apparatus and method for coupling devices to a PCI-to-PCI bridge in an
intelligent I/O controller The present invention pertains to an apparatus and method for transparently coupling PCI devices behind a PCI-to-PCI bridge. A controller is coupled to a primary... |
| US-6,094,203 |
Architecture for a graphics processing unit using main memory A CPU and a CPU cache memory unit is coupled to a system memory bus. A graphics processor with a graphics cache memory unit is also coupled to the system memory... |
| US-6,092,119 |
Random access audio/video processor with compressed video resampling to
allow higher bandwidth throughput A random access audio/video processor having multiple outputs is disclosed. The processor includes a main control unit with analog video and audio back panels,... |
| US-6,088,743 |
Processor receiving response request corresponding to access clock
signal with buffer for external transfer... A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a... |
| US-6,088,701 |
Command data transport to a graphics processing device from a CPU
performing write reordering operations A system and method for enabling a graphics processor to operate with a CPU that reorders write instructions without requiring expensive hardware and which does... |
| US-6,085,333 |
Method and apparatus for synchronization of code in redundant
controllers in a swappable environment Methods and associated apparatus for automatically synchronizing the operating code between a plurality of controllers. In a first embodiment after the spare... |
| US-6,085,332 |
Reset design for redundant raid controllers A reset circuit implemented in a RAID controller configured for dual active operation. The reset circuit generates a reset pulse with a relatively invariant... |
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