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Searching: cpu processor
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| Patent # | Description |
|---|---|
| US-6,226,722 |
Integrated level two cache and controller with multiple ports, L1 bypass
and concurrent accessing A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration,... |
| US-6,226,680 |
Intelligent network interface system method for protocol processing A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with... |
| US-6,222,548 |
Three-dimensional image processing apparatus An image processing system, including a main CPU, a main storage, a three-dimensional image processor and a CRT for a display unit. The system further includes a... |
| US-6,216,217 |
Data processor A data processor including: a CPU (1) for performing a wait operation upon input of a wait signal (10) to its wait terminal (9); a wait/wait cancel instruction... |
| US-6,216,190 |
System and method for optimally deferring or retrying a cycle upon a
processor bus that is destined for a... A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor... |
| US-6,212,589 |
System resource arbitration mechanism for a host bridge A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a... |
| US-6,212,134 |
Watch dog timer system A watch dog timer system which has an abnormality checking function of a high degree of reliability. In the watch dog timer system, abnormality of a computer... |
| US-6,211,890 |
Image processor and image processing method A main CPU 11, a main memory 12, a main DMAC (direct memory access controller) 13 and a picture processing unit (graphic processing unit or GPU) 15 are... |
| US-6,209,052 |
System and method for suppressing processor cycles to memory until after a
peripheral device write cycle is... A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus... |
| US-6,209,045 |
Data processor and data processing system A data processor has a ROM that holds a boot program for causing the CPU to transfer a debug program from a serial interface circuit to a debug-use RAM area.... |
| US-6,204,864 |
Apparatus and method having improved memory controller request handler A computer system includes one or more display devices, such as a cathode ray tube (CRT) or liquid crystal display (LCD) for providing a visible display to a... |
| US-6,204,793 |
Sigma-Delta CODEC system A system for processing Sigma-Delta CODEC. The system includes modulation/demodulation device, Bus, a software-controlled digital signal processor, and Virtual... |
| US-6,202,104 |
Processor having a clock driven CPU with static design A processor comprises a central processing unit being clock driven and having a static design. A memory is coupled with the central processing unit for storing... |
| US-6,199,142 |
Processor/memory device with integrated CPU, main memory, and full width
cache and associated method An integrated processor/memory device comprising a main memory, a CPU, and a full width cache. The main memory comprises main memory banks. Each of the main... |
| US-6,199,118 |
System and method for aligning an initial cache line of data read from an
input/output device by a central... A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked... |
| US-6,198,629 |
Circuit board and computer system for enhanced cooling A computer system including a chassis of substantially rectangular cross section suitable for receiving a circuit board. A rear face of the chassis includes... |
| US-6,196,919 |
Shooting game apparatus, method of performing shooting game, and
computer-readable recording medium storing... A CPU of a control system controls a signal processor to effect various calculations to move a player's spaceship on a projection display screen, orient the... |
| US-6,195,750 |
Method and apparatus for dynamic CPU reconfiguration in a system employing
logical processors A multiprocessor system having a plurality of CPUs that can be dynamically reconfigured between online and offline without system shutdown. The multiprocessor... |
| US-6,195,739 |
Method and apparatus for passing data among processor complex stages of a
pipelined processing engine A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor... |
| US-6,193,152 |
Modular signature and data-capture system and point of transaction payment
and reward system A modular signature and data capture device employs a standardized ISA bus, standardized communication ports, and standardized x86 CPU architecture to promote... |
| US-6,189,052 |
On-chip i/o processor supporting different protocols having on-chip
controller for reading and setting pins,... An on-chip i/o-processor for controlling and communication with peripheral devices, wherein an i/o processor core (12), comprising at least one pin controller... |
| US-6,185,597 |
Method and system for expanding a buried stack frame A method and system for growing stack frames is described. According to the invention, actual growth of a stack frame buried below the top of the stack is... |
| US-6,184,908 |
Method and apparatus for co-processing video graphics data To minimize CPU processing requirements for preparing and transferring data to a graphics processor, a graphics command processor is provided that supports... |
| US-6,178,465 |
Image processors for reading and outputting data An image processor which reads and outputs image data. Only by inputting a keyword which causes us to associate an image intuitively, the image processor... |
| US-6,175,889 |
Apparatus, method and system for a computer CPU and memory to high speed
peripheral interconnect bridge having... A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of registered peripheral component... |
| US-6,175,880 |
Sound board emulation using digital signal processor An improved audio-output device coupleable to a computer system, in which a DSP operating under software control emulates a common command interface. The command... |
| US-6,173,416 |
System and method for detecting errors using CPU signature A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a... |
| US-6,173,409 |
Real-time power conservation for electronic device having a processor A real-time power conservation apparatus and method for portable computers employs a monitor to determine whether a CPU may rest based upon a real-time sampling... |
| US-6,173,366 |
Load and store instructions which perform unpacking and packing of data
bits in separate vector and integer... A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a... |
| US-6,173,358 |
Computer system having dual bus architecture with audio/video/CD drive
controller/coprocessor having integral... A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive... |
| US-6,172,990 |
Media access control micro-RISC stream processor and method for
implementing the same Disclosed are methods and apparatus for processing packet data received from a physical layer. The processing is performed in-line while streaming packets to an... |
| US-6,169,892 |
Flow control of authentication triplet request for reducing usage time of a
central processor A method of requesting authentication triplets as a function of CPU processing time at a MSC. The MSC requests a new set of authentication triplets from an HLR... |
| US-6,167,509 |
Branch performance in high speed processor A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data... |
| US-6,163,851 |
Data processor A data processor including an alternative clock generator for generating, in a power saving mode, an alternative clock signal which is supplied to a peripheral... |
| US-6,163,829 |
DSP interrupt control for handling multiple interrupts A multi-processor system is provided having a processor array configured of a plurality of CPUs (20) that are disposed on a global bus (14). A VEM interface (18)... |
| US-6,161,162 |
Multiprocessor system for enabling shared access to a memory A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are... |
| US-6,161,159 |
Multimedia computer with integrated circuit memory An alternate route to improved multimedia performance without replacing the central processor unit (CPU) is presented, through the utilization of general-purpose... |
| US-6,158,656 |
Final accommodation device for power-source drop A method and apparatus for enabling a processor to execute processing routine even if a power-source voltage drop occurs during processing. When an ignition key... |
| US-6,158,023 |
Debug apparatus The present invention provides a debug apparatus that can set complex break conditions, minimize a time lag from the detection of a break event to the break an... |
| US-6,158,020 |
Remote jumper set and reset A client on a network is provided with auxiliary low power logic, at the network adapter, that is always active and simulates network traffic (e.g. Ethernet... |
| US-6,157,984 |
Integrated controller/processor for disc drive having direct memory
access A single chip integrated disc/servo controller and processor (CPU) for a disc drive reduces timing overhead associated with processor/controller/memory... |
| US-6,157,967 |
Method of data communication flow control in a data processing system
using busy/ready commands A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit... |
| US-6,157,397 |
AGP read and CPU wire coherency A method for graphics device read and processor write coherency receives a write request from a processor to write data to a storage element for a component to... |
| US-6,154,831 |
Decoding operands for multimedia applications instruction coded with
less number of bits than combination of... A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a... |
| US-6,154,830 |
Microprocessor On a microprocessor chip mounting a central processing unit (CPU) for controlling the entire operation of electronic equipment and a digital signal processor... |
| US-6,154,827 |
Data processor capable of high speed accessing A data processor capable of accessing data with the data processing capacity of a central processing unit (CPU), even if the data processing capacity of the CPU... |
| US-6,154,785 |
Inter-processor communication system An inter-processor communication system for a multi-processor environment wherein each processor has an associated processor system controller comprising an... |
| US-6,151,689 |
Detecting and isolating errors occurring in data communication in a
multiple processor system A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit... |
| US-6,147,863 |
Industrial computer An industrial computer including a passive backplane generally compliant with the PCI/ISA industrial standard promulgated by the PICMG technical committee, but... |
| US-6,145,102 |
Transmission of an error message over a network by a computer which
fails a self-test A computer may have a management bus installed, where the management bus is coupled to sensors which monitor status of components of the computer. The management... |
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