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Patent # Description
US-5,987,553 Adaptor board interconnection for a processor board and motherboard
A computer system includes a motherboard to which a selected one of various processor boards can be coupled via an adaptor. The boards include a CPU and a heat...
US-5,986,991 Computer-controlled game device with cassette ROM and CD-ROM
A processing device is provided with a disk coating port and a cassette or cartridge port both formed on a common top face or surface of the device sot hat a CD...
US-5,982,845 Forward projection and backprojection processor
A forward projector/backprojector (30) for a CT scanner (10) includes a VME interface (36) which loads data onto and off of the forward projector/backprojector...
US-5,982,814 Dynamic control of processor utilization by a host signal processing modem
A host signal processor (HSP) modem which includes procedures executed in response to interrupts has a CPU utilization control procedure which uses the numbers...
US-5,982,360 Adaptive-selection method for memory access priority control in MPEG processor
An adaptive-selection method for memory access priority control in MPEG processor. The processor has functional modules that include an input interface, a CPU,...
US-5,978,953 error detection and correction
A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A...
US-5,978,874 Implementing snooping on a split-transaction computer system bus
Snooping is implemented on a split transaction snooping bus for a computer system having one or many such buses. Circuit boards including CPU or other devices...
US-5,977,997 Single chip computer having integrated MPEG and graphical processors
A highly integrated, single chip computer system having not only a central-processing unit (CPU) but also specialized coprocessors. The specialized coprocessors,...
US-5,974,259 Data processing system and method of operation having input/output drivers with reduced power consumption and...
A data processing system has a memory bus and a system input/output (I/O) bus including I/O drivers. The memory and I/O buses are controlled by a central...
US-5,968,150 Processor element having a plurality of CPUs for use in a multiple processor system
A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU...
US-5,963,973 Multiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of...
A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for...
US-5,963,068 Fast start-up processor clock generation method and system
A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider...
US-5,961,641 Data processor and data processing system
A data processor has a ROM that holds a boot program for causing the CPU to transfer a debug program from a serial interface circuit to a debug-use RAM area....
US-5,959,280 Multi-standard optical disk reading apparatus and method of reading using same
An optical disk reading apparatus and method to provide an optical disk reading system which is able to reproduce encoded optical data from varied optical disk...
US-5,958,029 Method and system for efficient message validation
A communications processor (30) includes a DMA controller (34) and a module associated with a broadcast communications protocol such as a CAN module (50), both...
US-5,953,536 Software-implemented tool for monitoring power management in a computer system
A software-implemented tool for monitoring CPU power usage in a personal computer system, especially well-suited for use in battery-powered computers running a...
US-5,951,685 Computer system with system ROM including serial-access PROM coupled to an auto-configuring memory controller...
A computer system having a processor is provided with a memory controller serially coupled to a serial-access programmable read-only-memory ROM (PROM) through a...
US-5,950,227 CPU write-back cache coherency mechanism that transfers data from a cache memory to a main memory after access...
A writeback cache coherency control module that can allow systems that do not support cache, or support only writethrough cache, to operate with a processor that...
US-5,949,812 Method and system for conserving battery reserves in a navigation receiver by slowing and/or stopping the...
A battery-operated navigation satellite receiver with an antenna, a radio frequency stage, a down-converter, a digital signal processor and a microcomputer for...
US-5,944,805 System and method for transmitting data upon an address portion of a computer system bus during periods of...
A system and method are presented for transmitting data upon an address portion of a computer system bus during periods of maximum or near-maximum utilization of...
US-5,943,623 Integrated control and signal processing in a cellular telephone
Control functions are integrated into the digital signal processing (DSP) chip functioning as the central processor unit (CPU) for the subscriber's cellular...
US-5,943,421 Processor having compression and encryption circuitry
A data processing system (100) includes a data processor or CPU (102) having decompression circuitry (208, 212) and decryption circuitry (210, 214) that operates...
US-5,943,284 Semiconductor memory device
A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are...
US-5,941,938 System and method for performing an accumulate operation on one or more operands within a partitioned register
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-5,940,599 Data processor
A start signal is generated which selects, from among a plurality of sub-periods resulting from division of one cycle period of an external clock signal and each...
US-5,935,230 Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each...
At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such...
US-5,933,649 Method and device for controlling a CPU stop clock interrupt
A method and device for controlling a CPU stop clock interrupt of a computer system. The device includes an idle detector and a control processor. A CPU having a...
US-5,931,948 Portable computer system having password control means for holding one or more passwords such that the...
A portable computer system includes a keyboard for inputting at least a password, and a main CPU for controlling the system operation to perform a data...
US-5,929,868 Method and apparatus for computer display memory management
A method and an apparatus for interleaving display frame buffers is disclosed. The system includes a processor providing CPU addresses for peripheral (access, a...
US-5,925,133 Integrated processor system adapted for portable personal information devices
An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive...
US-5,925,125 Apparatus and method for pre-verifying a computer instruction set to prevent the initiation of the execution of...
A Test Operation-Code (TSTOP) instruction pre-verifies the validity of a target instruction op-code prior to execution of the target instruction. The...
US-5,925,105 Preventing processor domination during background data transfer in multipoint conferencing
Preventing processor domination of a CPU by background transfers of teleconference object data during an electronic conference is accomplished by monitoring an...
US-5,923,887 Interrupt request that defines resource usage
An improved programmable interrupt controller for use in a computer system including one or more interrupt service providers (ISPs), usually central processing...
US-5,920,302 Display scrolling circuit
A display scrolling circuit is provided which can give a variety to a display image by scrolling the display image for every display line without provision of a...
US-5,918,064 Data processing system having an input/output coprocessor with a separate visibility bus
A data processing system includes a central processing unit (CPU) (20), a peripheral bus (32), and an input/output (I/O) coprocessor (38). The CPU (20) and the...
US-5,918,045 Data processor and data processing system
The data processor includes a CPU and an instruction prefetch buffer that prefetches an instruction executed by the CPU and stores it therein. The CPU contains a...
US-5,916,312 ASIC having flexible host CPU interface for ASIC adaptable for multiple processor family members
A CPU interface having an 8-bit mode in which the interface is capable of interfacing with a host CPU having 8-bit data bus, and a 16-bit mode in which the...
US-5,916,296 Dual processor automotive control system having flexible processor standardization
To execute high-accuracy control employing communication data of a microprocessor while attempting standardization of the microprocessor, a host microprocessor...
US-5,915,236 Word recognition system which alters code executed as a function of available computational resources
A word recognition system detects the computational resources available to it, such as the speed or number of processors, or whether there is DSP hardware, and...
US-5,913,068 Multi-processor power saving system which dynamically detects the necessity of a power saving operation to...
A computer is constituted by a plurality of CPUs having the same power consumption and the same performance. A system controller has an interrupt control...
US-5,911,084 System and method for accessing peripheral devices on a non-functional controller
A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access...
US-5,911,052 Split transaction snooping bus protocol
A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other...
US-5,909,686 Hardware-assisted central processing unit access to a forwarding database
A method and apparatus for providing hardware-assisted CPU access to a forwarding database is described. According to one aspect of the present invention, a...
US-5,909,572 System and method for conditionally moving an operand from a source register to a destination register
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-5,909,422 Optical disk reading method for multi-layered optical disk system
A multi-layered optical disk reading method which makes possible to reproduce encoded data from each data layer by focusing laser beam precisely onto a data...
US-5,907,684 Independent channel coupled to be shared by multiple physical processing nodes with each node characterized as...
A computer system and processing method are provided for coupling multiple physical processing nodes together, wherein each physical processing node is...
US-5,905,910 System for multi-threaded disk drive operation in a computer system using an interrupt processor software...
A system for multi-threaded disk drive interrupt processing uses a flag register containing encoded data bits to indicate the current status of at least two disk...
US-5,900,869 Information processor system allowing multi-user editing
An information processor system includes a control unit for controlling the entire system mainly formed of a CPU, a display for displaying image data to be...
US-5,900,019 Apparatus for protecting memory storage blocks from I/O accesses
Apparatus for protecting memory storage blocks (page frames) against unwanted I/O accesses, including I/O data transferred in an unwanted direction. I/O storage...
US-5,900,011 Integrated processor/memory device with victim data cache
An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The...
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