Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: cpu processor





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-5,951,685 Computer system with system ROM including serial-access PROM coupled to an auto-configuring memory controller...
A computer system having a processor is provided with a memory controller serially coupled to a serial-access programmable read-only-memory ROM (PROM) through a...
US-5,950,227 CPU write-back cache coherency mechanism that transfers data from a cache memory to a main memory after access...
A writeback cache coherency control module that can allow systems that do not support cache, or support only writethrough cache, to operate with a processor that...
US-5,949,812 Method and system for conserving battery reserves in a navigation receiver by slowing and/or stopping the...
A battery-operated navigation satellite receiver with an antenna, a radio frequency stage, a down-converter, a digital signal processor and a microcomputer for...
US-5,944,805 System and method for transmitting data upon an address portion of a computer system bus during periods of...
A system and method are presented for transmitting data upon an address portion of a computer system bus during periods of maximum or near-maximum utilization of...
US-5,943,623 Integrated control and signal processing in a cellular telephone
Control functions are integrated into the digital signal processing (DSP) chip functioning as the central processor unit (CPU) for the subscriber's cellular...
US-5,943,421 Processor having compression and encryption circuitry
A data processing system (100) includes a data processor or CPU (102) having decompression circuitry (208, 212) and decryption circuitry (210, 214) that operates...
US-5,943,284 Semiconductor memory device
A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are...
US-5,941,938 System and method for performing an accumulate operation on one or more operands within a partitioned register
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-5,940,599 Data processor
A start signal is generated which selects, from among a plurality of sub-periods resulting from division of one cycle period of an external clock signal and each...
US-5,935,230 Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each...
At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such...
US-5,933,649 Method and device for controlling a CPU stop clock interrupt
A method and device for controlling a CPU stop clock interrupt of a computer system. The device includes an idle detector and a control processor. A CPU having a...
US-5,931,948 Portable computer system having password control means for holding one or more passwords such that the...
A portable computer system includes a keyboard for inputting at least a password, and a main CPU for controlling the system operation to perform a data...
US-5,929,868 Method and apparatus for computer display memory management
A method and an apparatus for interleaving display frame buffers is disclosed. The system includes a processor providing CPU addresses for peripheral (access, a...
US-5,925,133 Integrated processor system adapted for portable personal information devices
An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive...
US-5,925,125 Apparatus and method for pre-verifying a computer instruction set to prevent the initiation of the execution of...
A Test Operation-Code (TSTOP) instruction pre-verifies the validity of a target instruction op-code prior to execution of the target instruction. The...
US-5,925,105 Preventing processor domination during background data transfer in multipoint conferencing
Preventing processor domination of a CPU by background transfers of teleconference object data during an electronic conference is accomplished by monitoring an...
US-5,923,887 Interrupt request that defines resource usage
An improved programmable interrupt controller for use in a computer system including one or more interrupt service providers (ISPs), usually central processing...
US-5,920,302 Display scrolling circuit
A display scrolling circuit is provided which can give a variety to a display image by scrolling the display image for every display line without provision of a...
US-5,918,064 Data processing system having an input/output coprocessor with a separate visibility bus
A data processing system includes a central processing unit (CPU) (20), a peripheral bus (32), and an input/output (I/O) coprocessor (38). The CPU (20) and the...
US-5,918,045 Data processor and data processing system
The data processor includes a CPU and an instruction prefetch buffer that prefetches an instruction executed by the CPU and stores it therein. The CPU contains a...
US-5,916,312 ASIC having flexible host CPU interface for ASIC adaptable for multiple processor family members
A CPU interface having an 8-bit mode in which the interface is capable of interfacing with a host CPU having 8-bit data bus, and a 16-bit mode in which the...
US-5,916,296 Dual processor automotive control system having flexible processor standardization
To execute high-accuracy control employing communication data of a microprocessor while attempting standardization of the microprocessor, a host microprocessor...
US-5,915,236 Word recognition system which alters code executed as a function of available computational resources
A word recognition system detects the computational resources available to it, such as the speed or number of processors, or whether there is DSP hardware, and...
US-5,913,068 Multi-processor power saving system which dynamically detects the necessity of a power saving operation to...
A computer is constituted by a plurality of CPUs having the same power consumption and the same performance. A system controller has an interrupt control...
US-5,911,084 System and method for accessing peripheral devices on a non-functional controller
A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access...
US-5,911,052 Split transaction snooping bus protocol
A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other...
US-5,909,686 Hardware-assisted central processing unit access to a forwarding database
A method and apparatus for providing hardware-assisted CPU access to a forwarding database is described. According to one aspect of the present invention, a...
US-5,909,572 System and method for conditionally moving an operand from a source register to a destination register
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-5,909,422 Optical disk reading method for multi-layered optical disk system
A multi-layered optical disk reading method which makes possible to reproduce encoded data from each data layer by focusing laser beam precisely onto a data...
US-5,907,684 Independent channel coupled to be shared by multiple physical processing nodes with each node characterized as...
A computer system and processing method are provided for coupling multiple physical processing nodes together, wherein each physical processing node is...
US-5,905,910 System for multi-threaded disk drive operation in a computer system using an interrupt processor software...
A system for multi-threaded disk drive interrupt processing uses a flag register containing encoded data bits to indicate the current status of at least two disk...
US-5,900,869 Information processor system allowing multi-user editing
An information processor system includes a control unit for controlling the entire system mainly formed of a CPU, a display for displaying image data to be...
US-5,900,019 Apparatus for protecting memory storage blocks from I/O accesses
Apparatus for protecting memory storage blocks (page frames) against unwanted I/O accesses, including I/O data transferred in an unwanted direction. I/O storage...
US-5,900,011 Integrated processor/memory device with victim data cache
An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The...
US-5,898,894 CPU reads data from slow bus if I/O devices connected to fast bus do not acknowledge to a read request after a...
A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory...
US-5,898,829 Fault-tolerant computer system capable of preventing acquisition of an input/output information path by a...
In a computer system comprising first through N-th processors which are provided with first through N-th processor input/output information transmission paths,...
US-5,896,521 Processor synthesis system and processor synthesis method
The present invention provides a processor synthesis system and a processor synthesis method which enable a designer to synthesize a CPU that does not depend on...
US-5,895,492 Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system
Provides a processor CLE (CPU lock element) for each processor in a protected storage in a multi-processor computer system. Each CLE contains a blocking symbol...
US-5,893,154 CPU write-back cache coherency mechanism that transeers data from a cache memory to a main memory before access...
A writeback cache coherency control module that can allow systems that do not support cache, or support only writethrough cache, to operate with a processor that...
US-5,893,153 Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with...
An integrated processor includes an on-chip integrated input/output (IO) system (which does not have a on-chip bus) to handle direct memory access (DMA)...
US-5,893,145 System and method for routing operands within partitions of a source register to partitions within a...
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-5,892,980 System for dynamically changing the length of transmit and receive sample buffers utilizing previous responding...
An apparatus for and method of implementing a novel buffer based fall duplex communication system is disclosed. The disclosed invention is particularly useful in...
US-5,892,974 System for sub-data processor identifies the peripheral from supplied identification data and supplies data...
A data processing apparatus achieves high-speed image control, image control responding rapidly to the content of the operation of a peripheral, avoidance of...
US-5,890,220 Address conversion apparatus accessible to both I/O devices and processor and having a reduced number of index...
In a computer system having an address converter for DMA (direct memory access), an address conversion apparatus in which a memory area to be accessed by the DMA...
US-5,890,003 Interrupts between asynchronously operating CPUs in fault tolerant computer system
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory...
US-5,884,100 Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor
A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing...
US-5,884,092 System for maintaining fixed-point data alignment within a combination CPU and DSP system
In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having...
US-5,884,091 Computer system having a central processing unit responsive to the identity of an upgrade processor
A uniprocessing computer system is provided with an original CPU and an upgrade socket for receiving an additional processor that need not be of a single...
US-5,883,327 Keyboard system for an electric musical instrument in which each key is provided with an independent output to...
A keyboard system for an electronic musical instrument includes: a keyboard having a number of keys; a keyboard central processing unit (CPU) coupled to the...
US-5,880,855 Document process apparatus including a memory storage location function
A document processing apparatus that is adapted to the state of document data to be processed and performs document processing at low cost and efficiently. When...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.