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Searching: cpu processor





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Patent # Description
US-5,925,125 Apparatus and method for pre-verifying a computer instruction set to prevent the initiation of the execution of...
A Test Operation-Code (TSTOP) instruction pre-verifies the validity of a target instruction op-code prior to execution of the target instruction. The...
US-5,925,105 Preventing processor domination during background data transfer in multipoint conferencing
Preventing processor domination of a CPU by background transfers of teleconference object data during an electronic conference is accomplished by monitoring an...
US-5,923,887 Interrupt request that defines resource usage
An improved programmable interrupt controller for use in a computer system including one or more interrupt service providers (ISPs), usually central processing...
US-5,920,302 Display scrolling circuit
A display scrolling circuit is provided which can give a variety to a display image by scrolling the display image for every display line without provision of a...
US-5,918,064 Data processing system having an input/output coprocessor with a separate visibility bus
A data processing system includes a central processing unit (CPU) (20), a peripheral bus (32), and an input/output (I/O) coprocessor (38). The CPU (20) and the...
US-5,918,045 Data processor and data processing system
The data processor includes a CPU and an instruction prefetch buffer that prefetches an instruction executed by the CPU and stores it therein. The CPU contains a...
US-5,916,312 ASIC having flexible host CPU interface for ASIC adaptable for multiple processor family members
A CPU interface having an 8-bit mode in which the interface is capable of interfacing with a host CPU having 8-bit data bus, and a 16-bit mode in which the...
US-5,916,296 Dual processor automotive control system having flexible processor standardization
To execute high-accuracy control employing communication data of a microprocessor while attempting standardization of the microprocessor, a host microprocessor...
US-5,915,236 Word recognition system which alters code executed as a function of available computational resources
A word recognition system detects the computational resources available to it, such as the speed or number of processors, or whether there is DSP hardware, and...
US-5,913,068 Multi-processor power saving system which dynamically detects the necessity of a power saving operation to...
A computer is constituted by a plurality of CPUs having the same power consumption and the same performance. A system controller has an interrupt control...
US-5,911,084 System and method for accessing peripheral devices on a non-functional controller
A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access...
US-5,911,052 Split transaction snooping bus protocol
A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other...
US-5,909,686 Hardware-assisted central processing unit access to a forwarding database
A method and apparatus for providing hardware-assisted CPU access to a forwarding database is described. According to one aspect of the present invention, a...
US-5,909,572 System and method for conditionally moving an operand from a source register to a destination register
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-5,909,422 Optical disk reading method for multi-layered optical disk system
A multi-layered optical disk reading method which makes possible to reproduce encoded data from each data layer by focusing laser beam precisely onto a data...
US-5,907,684 Independent channel coupled to be shared by multiple physical processing nodes with each node characterized as...
A computer system and processing method are provided for coupling multiple physical processing nodes together, wherein each physical processing node is...
US-5,905,910 System for multi-threaded disk drive operation in a computer system using an interrupt processor software...
A system for multi-threaded disk drive interrupt processing uses a flag register containing encoded data bits to indicate the current status of at least two disk...
US-5,900,869 Information processor system allowing multi-user editing
An information processor system includes a control unit for controlling the entire system mainly formed of a CPU, a display for displaying image data to be...
US-5,900,019 Apparatus for protecting memory storage blocks from I/O accesses
Apparatus for protecting memory storage blocks (page frames) against unwanted I/O accesses, including I/O data transferred in an unwanted direction. I/O storage...
US-5,900,011 Integrated processor/memory device with victim data cache
An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The...
US-5,898,894 CPU reads data from slow bus if I/O devices connected to fast bus do not acknowledge to a read request after a...
A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory...
US-5,898,829 Fault-tolerant computer system capable of preventing acquisition of an input/output information path by a...
In a computer system comprising first through N-th processors which are provided with first through N-th processor input/output information transmission paths,...
US-5,896,521 Processor synthesis system and processor synthesis method
The present invention provides a processor synthesis system and a processor synthesis method which enable a designer to synthesize a CPU that does not depend on...
US-5,895,492 Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system
Provides a processor CLE (CPU lock element) for each processor in a protected storage in a multi-processor computer system. Each CLE contains a blocking symbol...
US-5,893,154 CPU write-back cache coherency mechanism that transeers data from a cache memory to a main memory before access...
A writeback cache coherency control module that can allow systems that do not support cache, or support only writethrough cache, to operate with a processor that...
US-5,893,153 Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with...
An integrated processor includes an on-chip integrated input/output (IO) system (which does not have a on-chip bus) to handle direct memory access (DMA)...
US-5,893,145 System and method for routing operands within partitions of a source register to partitions within a...
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a...
US-5,892,980 System for dynamically changing the length of transmit and receive sample buffers utilizing previous responding...
An apparatus for and method of implementing a novel buffer based fall duplex communication system is disclosed. The disclosed invention is particularly useful in...
US-5,892,974 System for sub-data processor identifies the peripheral from supplied identification data and supplies data...
A data processing apparatus achieves high-speed image control, image control responding rapidly to the content of the operation of a peripheral, avoidance of...
US-5,890,220 Address conversion apparatus accessible to both I/O devices and processor and having a reduced number of index...
In a computer system having an address converter for DMA (direct memory access), an address conversion apparatus in which a memory area to be accessed by the DMA...
US-5,890,003 Interrupts between asynchronously operating CPUs in fault tolerant computer system
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory...
US-5,884,100 Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor
A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing...
US-5,884,092 System for maintaining fixed-point data alignment within a combination CPU and DSP system
In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having...
US-5,884,091 Computer system having a central processing unit responsive to the identity of an upgrade processor
A uniprocessing computer system is provided with an original CPU and an upgrade socket for receiving an additional processor that need not be of a single...
US-5,883,327 Keyboard system for an electric musical instrument in which each key is provided with an independent output to...
A keyboard system for an electronic musical instrument includes: a keyboard having a number of keys; a keyboard central processing unit (CPU) coupled to the...
US-5,880,855 Document process apparatus including a memory storage location function
A document processing apparatus that is adapted to the state of document data to be processed and performs document processing at low cost and efficiently. When...
US-5,880,387 Digital sound processor having a slot assigner
A digital sound generating apparatus and sound generating method therefor is disclosed including a CPU interface for exchanging information with a CPU...
US-5,878,369 Golf course yardage and information system
A player position determining and course management system for a golf course having a plurality of roving units for use by players in playing the course is...
US-5,878,237 Apparatus, method and system for a comuter CPU and memory to PCI bridge having a pluarlity of physical PCI buses
A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of peripheral component interconnect ("PCI")...
US-5,878,217 Network controller for switching into DMA mode based on anticipated memory overflow and out of DMA mode when...
A network controller has a default non-DMA mode of data transfer that transfers received data frames to a desired location in internal memory under control of a...
US-5,872,960 Integrated circuit having CPU core operable for switching between two independent asynchronous clock sources of...
An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the...
US-5,870,713 Information processor
An information processor having a scheduling function according to the present invention includes an input device, a memory for storing elementary item...
US-5,864,704 Multimedia processor using variable length instructions with opcode specification of source operand as result...
A media engine is disclosed herein which incorporates into a single chip structure the seven multimedia functions of video, 2D graphics, 3D graphics, audio,...
US-5,864,702 Computer system power management interconnection circuitry, systems and methods
A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management...
US-5,862,308 Fault intercept and resolution process independent of operating system
A fault handling process in a computer system subject to CPU design errors and functioning under an operating system (OS) having an integral fault handling...
US-5,861,892 Image processing apparatus using compressed-data processing
An image processing apparatus in which image data is input, a generator generates area information and a processor processes the image data in accordance with...
US-5,860,148 Asynchronous transfer mode cell processing system with cell buffer space gathering
Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor provides a cell buffer RAM (CBR)...
US-5,860,032 Autofocus device of a camera and method
An autofocus device and method for a camera that can process statistically the tracking and focusing of an object in high velocity motion. The device and method...
US-5,860,000 Floating point unit pipeline synchronized with processor pipeline
An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the...
US-5,854,641 Method and apparatus for display image rotation
A method and an apparatus for rotating images on a computer system is disclosed. The system includes a processor for accessing an image frame buffer using a set...
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