Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: cpu processor





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,195,443 Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores
A compiler may optimize source code and any referenced libraries to execute on a plurality of different processor architecture implementations. For example, if...
US-9,189,828 Graphic processor based accelerator system and method
An accelerator system is implemented on an expansion card comprising a printed circuit board having (a) one or more graphics processing units (GPUs), (b) two or...
US-9,189,670 System and method for capturing and detecting symbology features and parameters
This invention provides a system and method for capturing, detecting and extracting features of an ID, such as a 1D barcode, that employs an efficient...
US-9,189,519 Executing database queries using multiple processors
A system and a method are disclosed for efficiently executing database queries using a computing device that includes a central processing unit (CPU) and a...
US-9,189,381 Managing CPU resources for high availability micro-partitions
A primary processing unit entitlement is determined for a logical partition. A smaller secondary processing unit entitlement is also determined. A partition...
US-9,189,267 Hardware virtualization for media processing
Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of...
US-9,183,402 Protecting secure software in a multi-security-CPU system
A computing system includes a first central processing unit (CPU) and a second CPU coupled with the first CPU and with a host processor. In response to a...
US-9,183,395 System and method for secure information handling system flash memory access
Firmware updates at an information handling system flash memory device, such as provisioning information stored on a USB device, are securely performed by using...
US-9,183,030 Virtual processor allocation techniques
One or more virtual processors can be added or removed from a virtual machine based on CPU pressure measured within the virtual machine. In addition to the...
US-9,182,984 Local clearing control
A computer implemented instruction is executed. One or more translation table entry locations (TLB) are specified by the instruction. Based on a local-clearing...
US-9,179,020 Handheld imaging device with integrated chip incorporating on shared wafer image processor and central processor
A handheld imaging device includes an image sensor for sensing an image; an integrated chip provided on a wafer substrate, the integrated chip integrating on...
US-9,178,820 Delayed auto new address learning
A network device includes a plurality of ports and at least one packet processor separate from a central processing unit (CPU). The packet processor is...
US-9,176,806 Computer and memory inspection method
In a memory inspection in a computer installing a x86 CPU, system software related to low-frequent processing is prevented from going down, and the suppression...
US-9,173,337 GNSS optimized control system and method
A GNSS system in combination with a hydraulically-actuated, airborne dispenser for a dry material crop dusting system to optimize the distribution of dry...
US-9,171,170 Data and key separation using a secure central processing unit
A computing system, comprising includes a first central processing unit (CPU) and a second CPU coupled with the first CPU and with a host processor. The second...
US-9,170,871 Data polling method and digital instrumentation and control system for atomic power plant using the method
The CPU includes: a data transmission instruction output processor; a failure detection signal input processor to which a failure detection signal is input from...
US-9,170,820 Syscall mechanism for processor to processor calls
Provided is a method for processing system calls from a GPU to a CPU. The method includes a GPU storing a plurality of tasks in a memory, with each task...
US-9,164,923 Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform
A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device (e.g., a graphics processing...
US-9,164,823 Resetting a peripheral driver and prohibiting writing into a register retaining data to be written into a...
An access method is executed by a multi-core processor system. The access method includes activating a driver that corresponds to a first CPU, based on a start...
US-9,164,804 Virtual memory module
A memory controller of a mass memory device determining that a memory operation has been initiated which involves the mass memory device, and in response...
US-9,158,916 Unauthorized access and/or instruction prevention, detection, and/or remediation, at least in part, by storage...
An embodiment may include a storage processor that may be comprised, at least in part, in a host. The host may include at least one host central processing unit...
US-9,158,628 Bios failover update with service processor having direct serial peripheral interface (SPI) access
Certain aspects direct to systems and methods of BIOS failover update with a service processor (SP) having direct serial peripheral interface (SPI) access to a...
US-9,158,564 Virtual service processor stack
Certain aspects of the present disclosure are directed to a computer system, including: a hypervisor configured to run on a CPU and to provide a first domain;...
US-9,158,470 Managing CPU resources for high availability micro-partitions
A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined...
US-9,158,344 CPU with stacked memory
A multi-chip package has a substrate with electrical contacts for connection to an external device. A CPU die is disposed on the substrate and is in...
US-9,149,656 Real-time three-dimensional radiation therapy apparatus and method
A radiation therapy apparatus including a robot supporting a robot head; a therapeutic radiation source attached to the robot head; a collimator for adjusting a...
US-9,148,669 High performance AVC encoder on a multi-core platform
A method and system for encoding a digital video signal using a plurality of parallel processors. A digital picture is received that is composed of one or more...
US-9,146,741 Eliminating redundant masking operations instruction processing circuits, and related processor systems,...
Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed....
US-9,128,721 Closed loop CPU performance control
The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves...
US-9,124,847 Video multiviewer system for generating video data based upon multiple video inputs with added graphic content...
A video multiviewer system may include a plurality of video inputs and a multiviewer video processor coupled to the plurality of video inputs. The multiviewer...
US-9,118,966 Enforcing software independent content protection in an electronic device during transcoding
A Set Top Box (STB) or client computer includes a communication interface operable to receive digital messages and digital content, memory, a transcoder, a...
US-9,117,449 Embedded system for construction of small footprint speech recognition with user-definable constraints
Techniques disclosed herein include systems and methods that enable a voice trigger that wakes-up an electronic device or causes the device to make additional...
US-9,111,409 Financial transactions processing system including cash automation machine
A financial transactions processing system includes a safe (cash automation machine) that performs transactions including at least one of receiving and...
US-9,111,050 Switching a computer system from a high performance mode to a low power mode
A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a...
US-9,104,485 CPU sharing techniques
Architectures and techniques for substantially maintaining performance of hyperthreads within processing cores of processors. One technique can include...
US-9,104,470 Task processor
A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage...
US-9,098,301 Electronic device and booting method
The present invention provides an electronic device including a write-once-then-read-only register, a chipset, a read-only memory, a flash memory and a central...
US-9,098,267 Analysis of short term CPU spikes in an operating system kernel
A profiler may analyze processes being run by a processor. The profiler may include logic to periodically sample a value of an instruction pointer that...
US-9,092,581 Virtualized communication sockets for multi-flow access to message channel infrastructure within CPU
A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A...
US-9,092,560 Trace based measurement architecture
A method for performing trace based measurement for a plurality of CPUs in parallel includes receiving a signal to perform a CPU parallel trace mode and...
US-9,088,474 Advanced processor with interfacing messaging network to a CPU
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is...
US-9,081,764 Iimplementing DMA migration of large system memory areas
A method, system and computer program product are provided for implementing memory migration of large system memory pages in a computer system. A large page to...
US-9,081,621 Efficient input/output-aware multi-processor virtual machine scheduling
Computerized methods, computer systems, and computer-readable media for governing how virtual processors are scheduled to particular logical processors are...
US-9,069,965 System and method for secure information handling system flash memory access
Firmware updates at an information handling system flash memory device, such as provisioning information stored on a USB device, are securely performed by using...
US-9,069,618 Updating kernal affinity for applications executing in a multiprocessor system
A multiprocessor system dynamically updates CPU affinities for processes executing on processors of the multiprocessor system based on an external signal. The...
US-9,058,170 Method and apparatus for adjusting a performance state of a processor resource
A method, apparatus or stored program for adjusting the clock throttle rate of a central processing unit (CPU) included in a computer, in which the usage of the...
US-9,053,027 Techniques for maintaining and restoring dirty caches across CPU resets
Described are techniques for performing caching. Write operations of a single transactions are received. Write data of the write operations is cached in one or...
US-9,052,959 Load balancing between general purpose processors and graphics processors
Disclosed are various embodiments for facilitating load balancing between central processing units (CPUs) and graphics processing units (GPUs). A request is...
US-9,052,948 Parallel runtime execution on multiple processors
A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or...
US-9,052,912 Data processor and control system
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.