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Searching: cpu processor





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Patent # Description
US-9,149,656 Real-time three-dimensional radiation therapy apparatus and method
A radiation therapy apparatus including a robot supporting a robot head; a therapeutic radiation source attached to the robot head; a collimator for adjusting a...
US-9,148,669 High performance AVC encoder on a multi-core platform
A method and system for encoding a digital video signal using a plurality of parallel processors. A digital picture is received that is composed of one or more...
US-9,146,741 Eliminating redundant masking operations instruction processing circuits, and related processor systems,...
Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed....
US-9,128,721 Closed loop CPU performance control
The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves...
US-9,124,847 Video multiviewer system for generating video data based upon multiple video inputs with added graphic content...
A video multiviewer system may include a plurality of video inputs and a multiviewer video processor coupled to the plurality of video inputs. The multiviewer...
US-9,118,966 Enforcing software independent content protection in an electronic device during transcoding
A Set Top Box (STB) or client computer includes a communication interface operable to receive digital messages and digital content, memory, a transcoder, a...
US-9,117,449 Embedded system for construction of small footprint speech recognition with user-definable constraints
Techniques disclosed herein include systems and methods that enable a voice trigger that wakes-up an electronic device or causes the device to make additional...
US-9,111,409 Financial transactions processing system including cash automation machine
A financial transactions processing system includes a safe (cash automation machine) that performs transactions including at least one of receiving and...
US-9,111,050 Switching a computer system from a high performance mode to a low power mode
A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a...
US-9,104,485 CPU sharing techniques
Architectures and techniques for substantially maintaining performance of hyperthreads within processing cores of processors. One technique can include...
US-9,104,470 Task processor
A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage...
US-9,098,301 Electronic device and booting method
The present invention provides an electronic device including a write-once-then-read-only register, a chipset, a read-only memory, a flash memory and a central...
US-9,098,267 Analysis of short term CPU spikes in an operating system kernel
A profiler may analyze processes being run by a processor. The profiler may include logic to periodically sample a value of an instruction pointer that...
US-9,092,581 Virtualized communication sockets for multi-flow access to message channel infrastructure within CPU
A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A...
US-9,092,560 Trace based measurement architecture
A method for performing trace based measurement for a plurality of CPUs in parallel includes receiving a signal to perform a CPU parallel trace mode and...
US-9,088,474 Advanced processor with interfacing messaging network to a CPU
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is...
US-9,081,764 Iimplementing DMA migration of large system memory areas
A method, system and computer program product are provided for implementing memory migration of large system memory pages in a computer system. A large page to...
US-9,081,621 Efficient input/output-aware multi-processor virtual machine scheduling
Computerized methods, computer systems, and computer-readable media for governing how virtual processors are scheduled to particular logical processors are...
US-9,069,965 System and method for secure information handling system flash memory access
Firmware updates at an information handling system flash memory device, such as provisioning information stored on a USB device, are securely performed by using...
US-9,069,618 Updating kernal affinity for applications executing in a multiprocessor system
A multiprocessor system dynamically updates CPU affinities for processes executing on processors of the multiprocessor system based on an external signal. The...
US-9,058,170 Method and apparatus for adjusting a performance state of a processor resource
A method, apparatus or stored program for adjusting the clock throttle rate of a central processing unit (CPU) included in a computer, in which the usage of the...
US-9,053,027 Techniques for maintaining and restoring dirty caches across CPU resets
Described are techniques for performing caching. Write operations of a single transactions are received. Write data of the write operations is cached in one or...
US-9,052,959 Load balancing between general purpose processors and graphics processors
Disclosed are various embodiments for facilitating load balancing between central processing units (CPUs) and graphics processing units (GPUs). A request is...
US-9,052,948 Parallel runtime execution on multiple processors
A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or...
US-9,052,912 Data processor and control system
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller...
US-9,047,471 Security enclave processor boot control
An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the...
US-9,047,078 Extract CPU time facility
An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that...
US-9,043,632 Security enclave processor power control
An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the...
US-9,043,627 Methods and apparatuses for controlling the temperature of a data processing system
Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system...
US-9,043,575 Managing CPU resources for high availability micro-partitions
A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined...
US-9,043,513 Methods and systems for mapping a peripheral function onto a legacy memory interface
A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and...
US-9,032,504 System and methods for an alternative to network controller sideband interface (NC-SI) used in out of band...
A system and a method for operating a plurality of information handling systems forming a network are provided. The system includes a host computer processing...
US-9,032,180 Managing CPU resources for high availability micro-partitions
A primary processing unit entitlement is determined for a logical partition. A smaller secondary processing unit entitlement is also determined. A partition...
US-9,030,943 Recovering from failures without impact on data traffic in a shared bus architecture
Methods of detecting and recovering from communication failures within an operating network switching device that is switching packets in a communication...
US-9,026,848 Achieving ultra-high availability using a single CPU
Techniques for achieving high-availability using a single processor (CPU). In a system comprising a multi-core processor, at least two partitions may be...
US-9,021,498 Adjusting pause-loop exiting window values
In a method for adjusting a Pause-loop exiting window value, one or more processors execute an exit instruction for a first virtual CPU (vCPU) in a virtualized...
US-9,021,497 Adjusting pause-loop exiting window values
In a method for adjusting a Pause-loop exiting window value, one or more processors execute an exit instruction for a first virtual CPU (vCPU) in a virtualized...
US-9,015,521 Method for switching a node controller link, processor system, and node
Embodiments of the present invention disclose a method for switching an NC link, a processor system, and a node, where the processor system includes more than...
US-9,009,726 Deterministic sharing of data among concurrent tasks using pre-defined deterministic conflict resolution policies
A "Concurrent Sharing Model" provides a programming model based on revisions and isolation types for concurrent revisions of states, data, or variables shared...
US-9,009,513 Multiprocessor for providing timers associated with each of processor cores to determine the necessity to...
Timers #0 through #3 are each supplied with a period for prohibiting a change in a power supply voltage. An OS #A or an OS #B determines necessity to change an...
US-9,009,223 Method and apparatus for processing received network packets on a network interface for a computer
An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a...
US-9,003,410 Abstracting a multithreaded processor core to a single threaded processor core
In an embodiment of the invention, an apparatus and method to abstract a multithreaded processor core to single threaded processor core include performing the...
US-8,997,113 Sharing virtual functions in a shared virtual memory between heterogeneous processors of a computing platform
A computing platform may include heterogeneous processors (e.g., CPU and a GPU) to support sharing of virtual functions between such processors. In one...
US-8,996,895 Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state...
A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the...
US-8,996,595 User activity response dynamic frequency scaling processor power management system and method
A method of executing a dynamic clock and voltage scaling (DCVS) algorithm in a central processing unit (CPU) is disclosed and may include monitoring CPU...
US-8,994,778 Systems and methods for providing video conferencing services via an ethernet adapter
The present application is directed towards systems and methods for providing video conference services via a single device installed as an Ethernet adapter on...
US-8,990,516 Multi-core shared memory system with memory port to memory space mapping
A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among...
US-8,987,873 Super integrated circuit chip semiconductor device
The CP555 Super Integrated Circuit Chip has a ceramic package casing made from (B4-C) Boron Carbide: a non-conducting ceramic material. The IC is connected to...
US-8,984,498 Variance analysis for translating CUDA code for execution by a general purpose processor
One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on...
US-8,984,183 Signaling, ordering, and execution of dynamically generated tasks in a processing system
One embodiment of the present invention sets forth a technique for enabling the insertion of generated tasks into a scheduling pipeline of a multiple processor...
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