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Searching: cpu processor





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Patent # Description
US-5,778,433 Computer system including a first level write-back cache and a second level cache
An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU...
US-5,778,423 Prefetch instruction for improving performance in reduced instruction set processor
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data...
US-5,778,252 On-board interface for concurrent seeks of multiple disk drives of a computer
An interface allows a given CPU (Central Processing Unit) to communicate concurrently with a large number of disk drives in a high-performance, low-cost system....
US-5,774,133 Computer system with improved pixel processing capabilities
A computer system having a pixel processing unit with multiple subprocessors receives positional data defining graphical objects from the CPU and writes pixel...
US-5,771,371 Method and apparatus for optimizing the display of forms in a data processing system
A method and apparatus for increasing efficiency in displaying characters on a display within the data processing system. A plurality of processes for displaying...
US-5,771,361 Data processor having shared terminal for monitoring internal and external memory events
In a data processor, an internal memory stores instruction codes and a central processing unit reads an instruction code form the memory and produces an external...
US-5,771,247 Low latency error reporting for high performance bus
A system and method are provided that use a determination of bad data parity and the state of an error signal (Derr.sub.--) as a functional signal indicating a...
US-5,767,866 Computer system with efficient DRAM access
A computer system includes one or more display devices, such as a cathode ray tube (CRT) or liquid crystal display (LCD) for providing a visible display to a...
US-5,765,197 Method and system for authentication of a memory unit for a computer system
A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive...
US-5,764,882 Multiprocessor system capable of isolating failure processor based on initial diagnosis result
A multiprocessor system containing a plurality of processor boards each having at least one processor, a CPU (central processing unit) which has malfunctioned...
US-5,764,809 Image processing apparatus using correlation among images
An image processing apparatus comprises a CPU, an information input unit, a main storage made up of a RAM, an image input interface, a display interface, and a...
US-5,764,505 Gas discharge laser control systems using multiple CPU's with shared memory on a common bus
A laser control system with multiple CPU's having shared memory on a common bus to provide high performance, relatively lost-cost, laser control. In the system...
US-5,761,698 Computer system having audio/video/CD drive controller/coprocessor having integral memory interface, graphics...
A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive...
US-5,761,444 Method and apparatus for dynamically deferring transactions
A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder...
US-5,758,113 Refresh control for dynamic memory in multiple processor system
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory...
US-5,757,365 Power down mode for computer system
A computer system includes a CPU and VGA/LCD controller interacting with a main system memory for processing input data and displaying it on an LCD panel screen...
US-5,754,883 System for controlling stop clock interrupt mode according to user selectable idle condition parameters and a...
A method and device for controlling a CPU stop clock interrupt of a computer system. The device includes an idle detector and a control processor. A CPU having a...
US-5,754,399 Direct coupled CPU package
An improved packaging scheme for a CPU of a main frame computer improves the performance while at the same reduces the cost of manufacture of the main frame...
US-5,754,165 Image sequence processor for personal computer
It is sought to display a pluralities of full motion image sequences together with personal computer texts, graphics, etc. on a personal computer display. NTSC...
US-5,751,955 Method of synchronizing a pair of central processor units for duplex, lock-step operation by copying data into...
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit...
US-5,751,932 Fail-fast, fail-functional, fault-tolerant multiprocessor system
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit...
US-5,751,886 Video image processing apparatus
A video image processing apparatus comprising with a frame memory for temporarily storing field video data from a recording medium, an interpolation processor...
US-5,751,375 Processing of pixel data at an operating frequency higher than the sampling rate of the input signal
A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA...
US-5,751,374 Processing of pixel data according to different broadcasting systems
A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA...
US-5,749,047 Method and apparatus for recognizing a test signal and determining signal transfer characteristics therefrom
A method and apparatus for fast response and distortion measurement of a signal transfer device. A computer processor generates a multitone test signal of...
US-5,748,630 Asynchronous transfer mode cell processing system with load multiple instruction and memory write-back
Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor includes a load multiple ...
US-5,748,001 Method and apparatus for fast response and distortion measurement
A method and apparatus for fast response and distortion measurement of a signal transfer device. A computer processor generates a multitone test signal of...
US-5,745,778 Apparatus and method for improved CPU affinity in a multiprocessor system
Closely related processing threads within a process in a multiprocessor system are collected into thread groups which are globally scheduled as a group based on...
US-5,745,757 Multiprocessor system with microprogrammed means for dispatching processes to processors
In a multiprocessor system, events capable of modifying the dispatching of processes to the processors (CPU, CPUi) start the execution of dispatching software...
US-5,745,728 Process or renders repeat operation instructions non-cacheable
A Central Processing Unit is provided having an instruction processor for determining CPU instruction types. An instruction detector is included in the CPU for...
US-5,745,580 Reduction of computational burden of adaptively updating control filter(s) in active systems
An active control method and apparatus for controlling vibration or sound wherein the computational burden to adaptively update the control filter within the...
US-5,742,849 High-performance computer system of a parallel write-buffering type
A computer system including a high speed CPU, a low speed main memory, and a system controller which has a write buffer coupled to the processor data bus in...
US-5,737,584 Data processing system having programmable external terminals such that the external terminals are selectively...
One or more of control bits (FIG. 7) are formed within a data processor (12) wherein the one or more control bits (FIG. 7) are programmable by the CPU (150) of...
US-5,734,845 Bus arbiter provided in a multi-processor system
In a multi-processor system in which a plurality of units such as a CPU serving as an information processing unit and an I/O control unit can be connected over a...
US-5,734,807 Image processing devices and methods
An image processing device displays an object having three-dimensional coordinates on a display as if the image of the object were viewed by a camera placed at a...
US-5,732,278 Data memory and processor bus
A data processing system has a CPU linked via a unidirectional read bus and a unidirectional write and address bus to a data memory (e.g., cache, RAM, or disk),...
US-5,732,224 Computer system having a dedicated multimedia engine including multimedia memory
A computer system optimized for real-time applications which provides increased performance for real-time applications over current computer architectures. The...
US-5,732,209 Self-testing multi-processor die with internal compare points
A microprocessor die contains several CPU cores that are substantially identical. A large second-level cache on the die is shared among the multiple CPU's. When...
US-5,729,767 System and method for accessing peripheral devices on a non-functional controller
A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access...
US-5,729,549 Simulcasting digital video programs for broadcast and interactive services
To provide interactivity, a public wireless packet data network is combined with a broadband digital broadcast network. In the preferred embodiment, the...
US-5,728,961 Method and device for executing tone generating processing depending on a computing capability of a processor used
In a tone generating method or device, where an arithmetic unit such as a CPU or DSP is used to execute a specific tone generating processing program to generate...
US-5,727,221 Computer system power management interconnection circuitry and systems
A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management...
US-5,727,216 Signal processor
A signal processor having excellent noise resistance characteristics while maintaining superior synchronizing characteristics for hardware interrupt processes....
US-5,724,551 Method for managing I/O buffers in shared storage by structuring buffer table having entries include storage...
A program stored on a portable storage medium for transferring the program from/to a data processing system, including to or from a disk medium in the system....
US-5,724,549 Cache coherency without bus master arbitration signals
A method of data communication between asynchronous processes of a computer system is disclosed in connection with a cache coherency system for a processor-cache...
US-5,719,958 System and method for image edge detection using discrete cosine transforms
The image processing system of the present invention provides electronic edge detection in keeping with ISO/JPEG/MPEG international compression standards for...
US-5,717,893 Method for managing a cache hierarchy having a least recently used (LRU) global cache and a plurality of LRU...
A method for managing a cache hierarchy having a fixed total storage capacity is disclosed. The cache hierarchy is logically partitioned to form a least recently...
US-5,717,854 Multimedia server having a plurality of stream controllers directly connected to the network
Each of processor units 31-1-31-n comprises a CPU, memory, and interface function. A high-speed communications network 32 interconnects the processor units for...
US-5,717,691 Multimedia network interface for asynchronous transfer mode communication system
A multimedia communications and computer platform that can serve as a network interface card combined with an internal distribution network for a full range of...
US-5,708,848 Paddle board interface for concurrent seeks on multiple disk drives of a computer
An interface allows a given CPU (Central Processing Unit) to communicate concurrently with a large number of disk drives in a high-performance, low-cost system....
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