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Searching: cpu processor





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Patent # Description
US-5,745,580 Reduction of computational burden of adaptively updating control filter(s) in active systems
An active control method and apparatus for controlling vibration or sound wherein the computational burden to adaptively update the control filter within the...
US-5,742,849 High-performance computer system of a parallel write-buffering type
A computer system including a high speed CPU, a low speed main memory, and a system controller which has a write buffer coupled to the processor data bus in...
US-5,737,584 Data processing system having programmable external terminals such that the external terminals are selectively...
One or more of control bits (FIG. 7) are formed within a data processor (12) wherein the one or more control bits (FIG. 7) are programmable by the CPU (150) of...
US-5,734,845 Bus arbiter provided in a multi-processor system
In a multi-processor system in which a plurality of units such as a CPU serving as an information processing unit and an I/O control unit can be connected over a...
US-5,734,807 Image processing devices and methods
An image processing device displays an object having three-dimensional coordinates on a display as if the image of the object were viewed by a camera placed at a...
US-5,732,278 Data memory and processor bus
A data processing system has a CPU linked via a unidirectional read bus and a unidirectional write and address bus to a data memory (e.g., cache, RAM, or disk),...
US-5,732,224 Computer system having a dedicated multimedia engine including multimedia memory
A computer system optimized for real-time applications which provides increased performance for real-time applications over current computer architectures. The...
US-5,732,209 Self-testing multi-processor die with internal compare points
A microprocessor die contains several CPU cores that are substantially identical. A large second-level cache on the die is shared among the multiple CPU's. When...
US-5,729,767 System and method for accessing peripheral devices on a non-functional controller
A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access...
US-5,729,549 Simulcasting digital video programs for broadcast and interactive services
To provide interactivity, a public wireless packet data network is combined with a broadband digital broadcast network. In the preferred embodiment, the...
US-5,728,961 Method and device for executing tone generating processing depending on a computing capability of a processor used
In a tone generating method or device, where an arithmetic unit such as a CPU or DSP is used to execute a specific tone generating processing program to generate...
US-5,727,221 Computer system power management interconnection circuitry and systems
A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management...
US-5,727,216 Signal processor
A signal processor having excellent noise resistance characteristics while maintaining superior synchronizing characteristics for hardware interrupt processes....
US-5,724,551 Method for managing I/O buffers in shared storage by structuring buffer table having entries include storage...
A program stored on a portable storage medium for transferring the program from/to a data processing system, including to or from a disk medium in the system....
US-5,724,549 Cache coherency without bus master arbitration signals
A method of data communication between asynchronous processes of a computer system is disclosed in connection with a cache coherency system for a processor-cache...
US-5,719,958 System and method for image edge detection using discrete cosine transforms
The image processing system of the present invention provides electronic edge detection in keeping with ISO/JPEG/MPEG international compression standards for...
US-5,717,893 Method for managing a cache hierarchy having a least recently used (LRU) global cache and a plurality of LRU...
A method for managing a cache hierarchy having a fixed total storage capacity is disclosed. The cache hierarchy is logically partitioned to form a least recently...
US-5,717,854 Multimedia server having a plurality of stream controllers directly connected to the network
Each of processor units 31-1-31-n comprises a CPU, memory, and interface function. A high-speed communications network 32 interconnects the processor units for...
US-5,717,691 Multimedia network interface for asynchronous transfer mode communication system
A multimedia communications and computer platform that can serve as a network interface card combined with an internal distribution network for a full range of...
US-5,708,848 Paddle board interface for concurrent seeks on multiple disk drives of a computer
An interface allows a given CPU (Central Processing Unit) to communicate concurrently with a large number of disk drives in a high-performance, low-cost system....
US-5,708,817 Programmable delay of an interrupt
A programmable interrupt delay in a communication circuit enables accurate timing of an interrupt delay without tying up processor CPU cycles in the execution of...
US-5,708,816 Method and apparatus for interrupt management for low power PDA
A method and system for operating a computer system in a low power mode in which the central processor unit (CPU) responds only to system events that require CPU...
US-5,706,514 Distributed execution of mode mismatched commands in multiprocessor computer systems
A technique for handling processor mode mismatched instructions or commands encountered by a CPU within a multiprocessor computer system. During thread...
US-5,706,489 Method for a CPU to utilize a parallel instruction execution processing facility for assisting in the...
A method for obtaining parallel instruction execution (PIE) for frequently used programming operations, such as database record compression or expansion,...
US-5,706,478 Display list processor for operating in processor and coprocessor modes
A processor for executing display list command packets in processor or coprocessor mode of execution. The processor dynamically switches between the two modes...
US-5,703,858 System for encoding a glass master to enable detection of a counterfeit optical CD-ROM
A device for enabling detection of a counterfeit optical CD-ROM is disclosed for use in a conventional mastering system. The device includes a signal source for...
US-5,701,450 System including ATA sequencer microprocessor which executes sequencer instructions to handle plurality of...
A modular ATA hard disc controller includes a small on-chip ATA sequencer microprocessor having on-chip dedicated hardware to manage real-time events without...
US-5,699,504 Multiprocessor system formed of a plurality of duplex processors
A multiprocessor system includes duplex processors, each duplex processor having two processors, one being active and the other being a stand-by processor. Each...
US-5,696,987 Hardware based interface for emulation of a standard system control processor
A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer....
US-5,692,119 Management method for a multiprocessor system
The number of instruction processors to be independently allocated to each supervisor is limited to a level at which the performance of the tightly coupled...
US-5,689,715 Low power ring detect for computer system wake-up
A computer system having a CPU, a power management processor, a modem, and a power supply in circuit communication. The power management processor controls the...
US-5,689,714 Method and apparatus for providing low power control of peripheral devices using the register file of a...
A method and apparatus for providing low power management of a data processing system (FIG. 1) involves a CPU (12) communicating to a register file (16) in a...
US-5,689,689 Clock circuits for synchronized processor systems having clock generator circuit with a voltage control...
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit...
US-5,689,431 Golf course yardage and information system
A player position determining and course management system for a golf course having a plurality of roving units for use by players in playing the course is...
US-5,684,993 Segregation of thread-specific information from shared task information
A multi-processor system includes memory and at least two central processing units (CPUs) that may execute different threads of computation of a same task at the...
US-5,682,552 Data communication adapter and data communication terminal apparatus for performing data transmission and...
In a data communication adapter apparatus for a digital data communication connected between a signal transmission path for transmitting both receive data and...
US-5,682,142 Electronic control system/network
A network system of programmable, identification, locating, monitoring and processing fixed position (FPN) and movable tag nodes, which provides direct...
US-5,680,641 Multiple register bank system for concurrent I/O operation in a CPU datapath
A system and method is provided for use in register-based CPUs for processing data in the CPU register bank while concurrently loading and unloading data into...
US-5,680,534 Video game/videographics program fabricating system and method with superimpose control
A videographics/video game fabricating system includes a multiprocessor based game processor console which includes a main central processing unit (CPU) which...
US-5,680,533 Videographics program/video game fabricating system and method
A videographics/video game fabricating system includes a multiprocessor based game processor console which includes a main central processing unit (CPU) which...
US-5,676,141 Electronic processor for pulse oximeters
An apparatus for measuring the concentration of blood constituents in which the architecture of the electronic processor reduces the amount of controller...
US-5,675,807 Interrupt message delivery identified by storage location of received interrupt data
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit...
US-5,675,763 Cache memory system and method for selectively removing stale aliased entries
A cache memory system and method for selectively removing stale "aliased" entries, which arise when portions of several address spaces are mapped into a single...
US-5,675,634 Announcement apparatus for switching system
An announcement apparatus for a switching system, comprising a host processor for controlling the output of announcement voices with respect to the total voice...
US-5,673,414 Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and...
In a computer system that contains an input output (I/O) bus connecting to I/O devices, a central processing unit (CPU), a CPU cache memory, a system memory not...
US-5,673,398 Data transfer control method, and peripheral circuit, data processor and data processing system for the method
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a...
US-5,669,003 Method of monitoring system bus traffic by a CPU operating with reduced power
A method for maintaining cache coherency while minimizing the power consumption. The method includes operating a first processor in a reduced power mode. While...
US-5,666,516 Protected programmable memory cartridge having selective access circuitry
A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive...
US-5,664,095 Dynamic scaling of CPU cycle consumption in a computer system
A method for dynamically scaling consumption of processor cycles by a task executing in a computer system, wherein a performance task determines an error measure...
US-5,663,804 Image processor having recording paper cutting control
Transportation of a document (P1), transportation of a recording sheet (P2), activation of a cutter system and simultaneous transportation of the document (P1)...
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