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Searching: cpu processor





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Patent # Description
US-5,615,327 Apparatus and method for controlling the initiating of a synchronization protocol for synchronizing a plurality...
A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of...
US-5,614,685 Digital signal processor for musical tone synthesizers and the like
When a digital signal processor (i.e., DSP) performs a data processing on data stored in a memory (e.g., RAM) in accordance with instructions given from a CPU,...
US-5,613,136 Locality manager having memory and independent code, bus interface logic, and synchronization components for a...
A method and an apparatus for reconciling communication and locality by enabling a user/programmer to write programs in an extended procedural language which...
US-RE35,480 Hardware based interface for mode switching to access memory above one megabyte
A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer....
US-5,611,073 Method of ensuring parameter coherency in a multi-processor system
In a multiprocessing machine having several processors which take turns in executing an instruction, processing of two related parameters in one processor takes...
US-5,611,070 Methods and apparatus for performing a write/load cache protocol
A Write/Load cache protocol is described which may be used for maintaining cache coherency and performing barrier synchronization in multiprocessor computer...
US-5,604,324 Musical tone signal generating apparatus including a plurality of voice units
A musical tone signal generating apparatus having a plurality of voice units connected to a common data bus to which a master central processing unit or master...
US-5,603,055 Single shared ROM for storing keyboard microcontroller code portion and CPU code portion and disabling access...
A shared keyboard and system ROM uses a single ROM for both the keyboard and the system operating system information (BIOS). The shared ROM is never...
US-5,603,038 Automatic restoration of user options after power loss
A computer system having a CPU, a non-volatile storage device, a power management processor having a volatile power management configuration, and a power supply...
US-5,603,017 Parallel integrated circuit having DSP module and CPU core operable for switching between two independent...
An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the...
US-5,599,231 Security systems and methods for a videographics and authentication game/program fabricating device
A videographics/video game fabricating system includes a multiprocessor based game processor console which includes a main central processing unit (CPU) which...
US-5,598,576 Audio output device having digital signal processor for responding to commands issued by processor by emulating...
An improved audio-output device coupleable to a computer system, in which a DSP operating under software control emulates a common command interface. The command...
US-5,598,553 Program watchpoint checking using paging with sub-page validity
Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a...
US-5,596,765 Integrated processor including a device for multiplexing external pin signals
An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive...
US-5,596,764 Debug mechanism for parallel-operating DSP module and CPU core
An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the...
US-5,594,864 Method and apparatus for unobtrusively monitoring processor states and characterizing bottlenecks in a...
Methods and apparatus are presented for unobtrusively monitoring processor states and characterizing bottlenecks in an arbitrary customer workload. An...
US-5,594,509 Method and apparatus for audio-visual interface for the display of multiple levels of information on a display
An interactive audio-visual (A/V) transceiver is advantageously coupled to a television and/or telephone (T/T) cable, a TV, a video recorder (VCR), and other A/V...
US-5,592,677 Integrated data processing system including CPU core and parallel, independently operating DSP module
An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the...
US-5,592,609 Video game/videographics program fabricating system and method with unit based program processing
A videographics/video game fabricating system includes a multiprocessor based game processor console which includes a main central processing unit (CPU) which...
US-5,590,375 Apparatus for performing concurrent seeks on plural integrated drive electronics (IDE) disk drives without...
An interface allows a given CPU (Central Processing Unit) to communicate concurrently with a large number of disk drives in a high-performance, low-cost system....
US-5,590,363 Circuit for detection of co-processor unit presence and for correction of its absence
A digital computer system includes a central processor unit (CPU) and an optional co-processor unit, both connected to a local bus. The co-processor unit, when...
US-5,590,362 Database engine predicate evaluator
A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing:...
US-5,590,357 Integrated CPU core and parallel, independently operating DSP module and time-critical core priority scheme
An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the...
US-5,588,131 System and method for a snooping and snarfing cache in a multiprocessor computer system
An improved multiprocessor computer system with an improved snarfing cache is disclosed. The multiprocessor system includes a main memory, I/O interface, and a...
US-5,588,111 Fault-tolerant computer system having switchable I/O bus interface modules
A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory...
US-5,586,308 Clock control unit responsive to a power management state for clocking multiple clocked circuits connected thereto
An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive...
US-5,586,284 Triple register RISC digital signal processor
The STREAMER FOR RISC DIGITAL SIGNAL PROCESSOR shown herein allows a CPU 46 to interface with a memory 60 via data registers 50. Pre-fetch and post-store of the...
US-5,584,031 System and method for executing a low power delay instruction
A system and method is provided for executing a low power no operation instruction in a data processor (10) with a minimal amount of power consumption. In the...
US-5,583,560 Method and apparatus for audio-visual interface for the selective display of listing information on a display
An interactive audio-visual (A/V) transceiver is advantageously coupled to a television and/or telephone (T/T) cable, a TV, a video recorder (VCR), and other A/V...
US-5,583,506 Signal processing system and method
An avionic digital signal processing system for a plurality of different types of input sensors such as radar, electro-optical, and electronic warfare that...
US-5,581,727 Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear...
An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU...
US-5,579,504 Multi-processor computer system having shared memory, private cache memories, and invalidate queues having...
Multi-processor systems are often implemented using a common system bus as the communication mechanism between CPU, memory, and I/O adapters. It is also common...
US-5,577,260 Data processing system having a serial interface comprising an end-of-transmission flag
In a data processor including a serial interface, the serial interface internally includes a transmission end flag formed of a RS flipflop which set in response...
US-5,574,847 Computer graphics parallel system with temporal priority
Front end processors in a graphics architecture execute parallel scan conversion and shading to process individually assigned primitive objects for providing...
US-5,574,770 Method for controlling overload of main processor of distributed switching system with hierarchy structure
A method for controlling an overload of a main processor by assigning to the main processor of a distributed switching system with a hierarchy structure a...
US-5,572,566 X-ray imaging apparatus and X-ray generation detector for activating the same
An image processor comprises a CPU, a ROM for storing programs and data, a main storage memory for storing image data, parameters for image processing and the...
US-5,568,624 Byte-compare operation for high-performance processor
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data...
US-5,568,622 Method and apparatus for minimizing the number of control words in a brom control store of a microprogrammed...
Method and apparatus to reduce the number of control words stored in a read only control store of a microprogrammed unit of the CPU of a large scale computer. A...
US-5,568,617 Processor element having a plurality of processors which communicate with each other and selectively use a...
A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU...
US-5,566,352 Register-read acknowledgment and prioritization for integration with a hardware-based interrupt acknowledgment...
A register-based computer architecture is particularly suited for using a common resource, such as a host processor or CPU, to respond to multiple devices such...
US-5,566,345 SCSI bus capacity expansion controller using gating circuits to arbitrate DMA requests from a plurality of disk...
In a data processing system having a data processor coupled to a SCSI channel disposed for transmitting and receiving data between the data processor and a...
US-5,561,822 System status maintaining and supporting apparatus sharing one console with a CPU
A system status maintaining and supporting apparatus in which more than two boards can be utilized with one console for communication, capable of monitoring the...
US-5,561,783 Dynamic cache coherency method and apparatus using both write-back and write-through operations
A dynamic cache coherency method and apparatus providing enhanced microprocessor system performance are described. The method and apparatus are advantageously...
US-5,561,779 Processor board having a second level writeback cache system and a third level writethrough cache system which...
A computer system which utilizes processor boards including a first level cache system integrated with the microprocessor, a second level external cache system...
US-5,560,023 Automatic backup system for advanced power management
A suspend/resume computer system having a CPU, a non-volatile storage device, volatile registers and memory data, a power management processor, a backup suspend...
US-5,559,952 Display controller incorporating cache memory dedicated for VRAM
A frame buffer cache is arranged to store part of image data in an image memory so that a CPU and a drawing processor can perform image data read/write...
US-5,557,769 Mechanism and protocol for maintaining cache coherency within an integrated processor
An integrated processor includes CPU core, cache memory, and cache controller coupled to a local bus via a local bus interface. The integrated processor further...
US-5,557,766 High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous...
A processor includes a bank-structured memory and is capable of handling multiple interrupts. The processor includes a central processing unit (CPU) comprising a...
US-5,555,395 System for memory table cache reloads in a reduced number of cycles using a memory controller to set status...
A method and apparatus for reducing the latency of TLB and segment descriptor reloads by eliminating the extra read/write cycles normally required for these...
US-5,555,197 Video signal processor and method for processing a scanning line regardless of the synchronizing signal
A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA...
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