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Searching: cpu processor





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Patent # Description
US-5,561,822 System status maintaining and supporting apparatus sharing one console with a CPU
A system status maintaining and supporting apparatus in which more than two boards can be utilized with one console for communication, capable of monitoring the...
US-5,561,783 Dynamic cache coherency method and apparatus using both write-back and write-through operations
A dynamic cache coherency method and apparatus providing enhanced microprocessor system performance are described. The method and apparatus are advantageously...
US-5,561,779 Processor board having a second level writeback cache system and a third level writethrough cache system which...
A computer system which utilizes processor boards including a first level cache system integrated with the microprocessor, a second level external cache system...
US-5,560,023 Automatic backup system for advanced power management
A suspend/resume computer system having a CPU, a non-volatile storage device, volatile registers and memory data, a power management processor, a backup suspend...
US-5,559,952 Display controller incorporating cache memory dedicated for VRAM
A frame buffer cache is arranged to store part of image data in an image memory so that a CPU and a drawing processor can perform image data read/write...
US-5,557,769 Mechanism and protocol for maintaining cache coherency within an integrated processor
An integrated processor includes CPU core, cache memory, and cache controller coupled to a local bus via a local bus interface. The integrated processor further...
US-5,557,766 High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous...
A processor includes a bank-structured memory and is capable of handling multiple interrupts. The processor includes a central processing unit (CPU) comprising a...
US-5,555,395 System for memory table cache reloads in a reduced number of cycles using a memory controller to set status...
A method and apparatus for reducing the latency of TLB and segment descriptor reloads by eliminating the extra read/write cycles normally required for these...
US-5,555,197 Video signal processor and method for processing a scanning line regardless of the synchronizing signal
A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA...
US-5,553,236 Method and apparatus for testing a clock stopping/starting function of a low power mode in a data processor
A processor (10) has an internal clock circuit (12), a CPU (14), and a test controller (16). The CPU (14) has a low-power mode of operation and a normal mode of...
US-5,553,228 Accelerated interface between processors and hardware adapters
Overall graphics performance in a computer graphics system is improved by an accelerated interface between high performance microprocessors and hardware adapters...
US-5,550,999 Information processing system which can check secondary storage medium having prescribed relation therewith and...
This invention provides an information processing system for a secondary storage medium which can prevent illegitimate reproduction of secondary storage media...
US-5,548,769 Database engine
A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing:...
US-5,548,711 Method and apparatus for fault tolerant fast writes through buffer dumping
An array controller including a DATA-RAM and a SHADOW-RAM. Both the DATA-RAM and the SHADOW-RAM are coupled to a first and second memory interface. Each memory...
US-5,546,563 Single chip replacement upgradeable computer motherboard with enablement of inserted upgrade CPU chip
A computer system is made capable of accepting more than one type of central processor including a plurality of sockets for receiving more than one type of...
US-5,546,547 Memory bus arbiter for a computer system having a dsp co-processor
An arbitration scheme for a computer system in which a digital signal processor resides on the computer system's memory bus without requiring a block of...
US-5,546,397 High reliability access point for wireless local area network
A high reliability access point for RF communications in a wireless local area network. The high reliability access point includes a central processing unit...
US-5,546,306 Multiple processor throttle control apparatus for an internal combustion engine
An electronic control apparatus for an engine of a vehicle has a first CPU for fuel control which controls the amount of fuel to be supplied to the engine and a...
US-5,544,344 Apparatus for caching smram in an intel processor based computer system employing system management mode
An apparatus and method for caching SMRAM in an Intel.RTM. CPU employing system management mode. A cache for the CPU includes a plurality of data entries and an...
US-5,544,341 Data access apparatus for preventing further cache access in case of an error during block data transfer
A data processor and method for preventing access to a cache memory when an abnormality occurs during a block data transfer. The data processor is provided with...
US-5,543,940 Method and apparatus for converting color scanner signals into colorimetric values
A method and apparatus for reconstructing a spectrum realizable in a medium from signals of a color scanner, includes the steps of obtaining an initial spectrum...
US-5,542,075 Method and apparatus for improving performance of out of sequence load operations in a computer system
The invention provides for improved performance of out of sequence load operations. The system has an improved compiler, with an optimizer, an improved CPU with...
US-5,542,064 Data read/write method by suitably selecting storage units in which multiple copies of identical data are...
When a CPU serving as a higher rank apparatus issues an input command to a secondary storage device having a plurality of disk drives, a predetermined number of...
US-5,542,059 Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time...
A CPU pipeline is able to process instructions from a complex instruction set computer CISC instruction set and from a reduced instruction set computer RISC set....
US-5,541,850 Method and apparatus for forming an integrated circuit including a memory structure
A set of circuit specifications including an internal memory structure is developed and then described in a hardware description language that is entered into a...
US-5,539,913 System for judging whether a main processor after processing an interrupt is required to process the I/O...
An information processing system according to the present invention judges whether or not an interruption accepted at a local processor for input/output control...
US-5,537,622 Database engine
A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing:...
US-5,537,604 Database engine
A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing:...
US-5,537,603 Database engine
A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing:...
US-5,537,602 Process system for controlling bus system to communicate data between resource and processor
A processor system includes an external resource, and a main CPU with a built-in bus control mechanism outputting an address bus and control signals and having a...
US-5,537,575 System for handling cache memory victim data which transfers data from cache to the interface while CPU...
A method and apparatus in a computer system for handling cache memory victim data for updating main memory. The invention operates in a computer system having...
US-5,537,544 Portable computer system having password control means for holding one or more passwords such that the...
A portable computer system includes a keyboard for inputting at least a password, and a main CPU for controlling the system operation to perform a data...
US-5,535,414 Secondary data transfer mechanism between coprocessor and memory in multi-processor computer system
A computer system having a CPU, a memory subcircuit, a peripheral subcircuit, a primary SCSI controller, which generates a SCSI bus, a coprocessor, and a...
US-5,535,339 Dual processor controlled compact disk-interactive system
A compact disk-interactive (CD-I) system which can reproduce CD-ROMs programmed using different codes as well as general compact disks for use as a multimedia...
US-5,535,137 Random access audio/video processor with compressed video resampling to allow higher bandwidth throughput
A random access audio/video processor having multiple outputs is disclosed. The processor includes a main control unit with analog video and audio back panels,...
US-5,530,899 Archival and retrieval system accessing an external storage by polling internal queues from remote terminals...
An archival and retrieval system which is connected to a host computer through an asynchronous serial line. The system operates unassisted through this serial...
US-5,530,893 System for selectively communicating information between processor and built-in keyboard and external input means
A data processing system having a built-in keyboard and an external input device which are alternately activated. If there is no command from the external...
US-5,530,889 Hierarchical structure processor having at least one sub-sequencer for executing basic instructions of a macro...
A hierarchical structure processor including a memory for storing processing instruction code data described sequentially; a main CPU for fetching and decoding...
US-5,530,883 Database engine
A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing:...
US-5,530,879 Computer system having power management processor for switching power supply from one state to another...
A computer system having a CPU, a power management processor, a switch, a modem, a timer, an override circuit, a glitch circuit, and a power supply in circuit...
US-5,530,877 Apparatus for providing continuity of operation in a computer
An apparatus for providing continuity of operation in system which performs a process having CPU, input/output, main memory and power supply by restoring the...
US-5,526,495 Bus control system in a multi-processor system
A bus arbiter permits an answer transfer request to utilize a system bus with higher priority than a command transfer request, thereby increasing the processing...
US-5,526,487 System for multiprocessor communication
A system for interprocessor communication including a shared register resource accessible by any one of the processors through the using internal communication...
US-5,522,058 Distributed shared-memory multiprocessor system with reduced traffic on shared bus
A distributed shared-memory multiprocessor system capable of reducing a traffic on the shared bus, without imposing any constraint concerning the types of...
US-5,519,879 Integrated circuit having CPU and DSP for executing vector lattice propagation instruction and updating values...
An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the...
US-5,517,556 Call processing system with facsimile processing
An improved telephone call processing apparatus for processing facsimile messages. The facsimile processing apparatus comprises a message control system...
US-5,515,529 Central processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit...
In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single...
US-5,513,358 Method and apparatus for power-up state initialization in a data processing system
A method and apparatus for implementing a power-up state initialization. A power sense circuit provides a signal for indicating when the power supply, V.sub.DD,...
US-5,513,255 Method for controlling overload of distributed processors of full electronic switching system
A method for controlling an overload of distributed processors of a full electronic switching system, capable of automatically calculating the number of calls to...
US-5,511,219 Mechanism for implementing vector address pointer registers in system having parallel, on-chip DSP module and...
An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the...
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