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Searching: cpu processor





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Patent # Description
US-5,491,828 Integrated data processing system having CPU core and parallel independently operating DSP module utilizing...
An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the...
US-5,491,799 Communication interface for uniform communication among hardware and software units of a computer system
A SYStem COMmunication interface (SYSCOM) unit provides uniform communication between hardware and software units of a computer system. The computer units...
US-5,491,793 Debug support in a processor chip
A central processing unit (CPU) with facilities for debug support. The debug support facilities include debug support unit (DSU), a debug support interface bus,...
US-5,491,788 Method of booting a multiprocessor computer where execution is transferring from a first processor to a second...
A multiprocessor computer system handles the failure of one or more of its processors without totally disabling the system. On power up, all of the CPUs are...
US-5,490,279 Method and apparatus for operating a single CPU computer system as a multiprocessor system
A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The...
US-5,490,096 Visual simulation apparatus
A CPU is connected to a memory storing programs for operating the CPU and a number of simulators, a display unit and a mouse for pointing a particular data shown...
US-5,488,710 Cache memory and data processor including instruction length decoding circuitry for simultaneously decoding a...
A cache memory, and a data processor including the cache memory, for processing at least one variable length instruction from a memory and outputting processed...
US-5,488,688 Data processor with real-time diagnostic capability
A data processor (20) includes a diagnostic circuit (23) with a first-in, first-out memory (FIFO) (25) for storing sequential states of an internal bus, such as...
US-5,487,173 DTMF detection in an integrated data processing system
The present invention is directed to an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a...
US-5,485,623 Information processor having high speed and safety resume system
An information processor operating with a battery writes data which exists in a register of a CPU at that time into a predetermined stack area for transfer of an...
US-5,485,602 Integrated circuit having a control signal for identifying coinciding active edges of two clock signals
A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs...
US-5,485,576 Chassis fault tolerant system management bus architecture for a networking
A fault tolerant system management bus architecture for a networking chassis includes a primary path for transmission of system management information and a...
US-5,481,689 Conversion of internal processor register commands to I/O space addresses
A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of...
US-5,481,663 Word processors for performing an automatic layout process
A word processor with an automatic layout function which automatically moves a possible figure, related to a text of a document to be moved in an automatic...
US-5,479,626 Signal processor contexts with elemental and reserved group addressing
The signal processor including a CPU 10 which selects a context register 16, the contents of which configure an address generator 20 and a data type converter...
US-5,475,315 Method and apparatus for fast response and distortion measurement
A method and apparatus for fast response and distortion measurement of a signal transfer device. A computer processor generates a multitone test signal of...
US-5,473,264 Methods and apparatus for electrically terminating a high speed communications pathway
A circuit arrangement and methods for sensing whether line terminator devices are present at terminal ends of high speed communications pathways, and enabling a...
US-5,471,601 Memory device and method for avoiding live lock of a DRAM with cache
A method and apparatus for allowing two or more masters, such as central processing units (CPUs), to read a dynamic random access memory (DRAM) device which...
US-5,471,405 Apparatus for measurement of forces and pressures applied to a garment
To provide a pair of shoes responsive to the relative forces applied to a wearer's feet, at least one force sensor is provided in each of a left and right shoe....
US-5,467,465 Two clock method for synchronizing a plurality of identical processors connected in parallel
A method to simplify the use of a plurality of identical processors connected in parallel. The method contains the steps of: (a) obtaining a computer system...
US-5,467,412 Correcting digitized signals to achieve specified output results for an image
An operator input subsystem and an image signal processing subsystem are provided to a digital image processing system. The operator input subsystem comprises a...
US-5,459,852 Cache bypass system with simultaneous initial transfer of target data to both processor and cache
A data processor which accesses a memory system only by a block transfer mode for transferring multiple data from the memory system when a cache misses a CPU...
US-5,459,763 Navigation message receiver for global positioning system
Signals representing navigation messages from four GPS artificial satellites are received by a GPS receiver and supplied to receiving processors of respective...
US-5,455,834 Fault tolerant address translation method and system
A method and system are disclosed wherein error detection codes are used for detecting and handling hardware errors in a memory table. Before each address and...
US-5,454,091 Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be...
A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only...
US-5,450,576 Distributed multi-processor boot system for booting each processor in sequence including watchdog timer for...
A system for controlling initialization and self test operations in a multiprocessor system facilitates the use of central processing units based around...
US-5,442,802 Asynchronous co-processor data mover method and means
Virtual addressing is available to a co-processor to asynchronously control the movement of multiple page units of data between different locations in the same...
US-5,442,797 Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging
A method and an apparatus for reconciling communication and locality by enabling a user/programmer to write programs in an extended procedural language which...
US-5,442,796 Pulse generator and demodulator with controlling processor and decrementing counters
A central processing unit (CPU) and a dedicated pulse generating and demodulating logic circuit are used to both generate and demodulate a wide variety of pulse...
US-5,442,764 Digital signal processing having improved execution efficiency
A digital signal processor (32) having an associated memory (34) executes a program interpreter (40) which interprets program routines stored in a program...
US-5,442,164 Bar code reader for reading two-dimensional bar codes by using length information derived from a sensed signal
The image of a bar code on a bar code label is picked up by a linear sensor while scanning in the X and Y directions is performed by a stage. An analog video...
US-5,440,750 Information processing system capable of executing a single instruction for watching and waiting for writing of...
Each processor of a multiprocessor system which shares a main storage has a execution circuit for executing a compare and watch instruction provided for watching...
US-5,440,710 Emulation of segment bounds checking using paging with sub-page validity
Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a...
US-5,440,697 Method and apparatus for simulating I/O devices
A computer system comprises a CPU, a main memory, and plurality of I/O Processors (IOPs), coupled to each other by a system I/O bus. The IOPs perform slave...
US-5,437,021 Programmable dedicated timer operating on a clock independent of processor timer
A hardware timer dedicated to the BIOS which operates independent of the CPU timer. The BIOS activates the timer by writing a delay count to a predetermined...
US-5,434,997 Method and apparatus for testing and debugging a tightly coupled mirrored processing system
A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus,...
US-5,430,853 Update of control parameters of a direct memory access system without use of associated processor
A DMA transfer control system includes a DMA control unit connected to a bus shared by a CPU; a storage device for receiving and storing various parameters of...
US-5,430,607 Rugged modular portable computer including modules hinged along an edge
A portable computer includes a processor, processor associated memory and control circuitry, and a memory disk drive assembly for storing software programs to...
US-5,428,761 System for achieving atomic non-sequential multi-word operations in shared memory
A computer system provides transactional memory operations, in which a selected data item in a shared memory is referenced by a CPU in local storage (such as a...
US-5,423,024 Fault tolerant processing section with dynamically reconfigurable voting
A fault-tolerant digital data processor includes three identical logic CPU boards connected to a voting bus and a system bus. The three boards are initially...
US-5,420,516 Method and apparatus for fast response and distortion measurement
A method and apparatus for fast response and distortion measurement of a signal transfer device. A computer processor generates a multitone test signal of...
US-5,418,973 Digital computer system with cache controller coordinating both vector and scalar operations
A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit,...
US-5,418,970 Parallel processing system with processor array with processing elements addressing associated memories using...
A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and...
US-5,416,783 Method and apparatus for generating pseudorandom numbers or for performing data compression in a data processor
A method and apparatus for generating pseudo-random numbers or for performing data compression in a data processor (12). In one form, the present invention...
US-5,416,497 Video display control system for animation pattern image
A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly ...
US-5,414,328 Stage lighting control console including assignable macro functions
A control console for controlling stage lighting includes a panel on which there are mounted a multiplicity of control elements in the form of switches, slider...
US-5,410,710 Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems
A multiprocessor programmable interrupt controller system, for use in a multiprocessor system in which one processor unit is a functional redundant checking...
US-5,410,682 In-register data manipulation for unaligned byte write using data shift in reduced instruction set processor
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data...
US-5,408,647 Automatic logical CPU assignment of physical CPUs
A multiprocessor computer system includes fault tolerant power up logic for finding a functioning CPU to operate as logical CPU0. Each microprocessor has a...
US-5,408,604 Display control integrated circuit for a display having an input panel
An input panel interface section is responsive to an input signal from an input panel to provide input coordinate data indicating an input position in a...
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