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Searching: cpu processor





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Patent # Description
US-5,321,823 Digital processor with bit mask for counting registers for fast register saves
A high-performance, pipelined CPU in which an improved method is used for saving registers in memory upon the occurrence of a procedure CALL or RETURN. The...
US-5,321,806 Method and apparatus for transmitting graphics command in a computer graphics system
A residue buffer, for temporary storage of portions of transmissions from a CPU to a graphics processor. Graphics commands are transmitted, in transmission units...
US-5,321,505 Computer scalable visualization system
A scalable visualization system includes a plurality of scalable tiles (10) that each comprise a display portion (18) and a processing portion (20). Each of the...
US-5,317,752 Fault-tolerant computer system with auto-restart after power-fall
A fault-tolerant computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly...
US-5,317,726 Multiple-processor computer system with asynchronous execution of identical code streams
A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs...
US-5,317,720 Processor system with writeback cache using writeback and non writeback transactions stored in separate queues
A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough)...
US-5,317,715 Reduced instruction set computer system including apparatus and method for coupling a high performance RISC...
Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of...
US-5,315,694 High-speed color saturation converter for digital color data
A high-speed saturation converter for a color image, comprising first R, G, and B image memories for storing digital color image data separated into R, G, and B,...
US-5,311,458 CPU with integrated multiply/accumulate unit
An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a...
US-5,307,464 Microprocessor and method for setting up its peripheral functions
A single chip microprocessor 1 includes a CPU 2 and a sub-processor 5 for software implementation of peripheral functions of the microprocessor 1. Sub-processor...
US-5,305,460 Data processor
In a microcomputer having two program execution states including a supervisor state and a user state, there is disposed a flag or a register having such a flag...
US-5,303,342 Method and apparatus for assembling a composite image from a plurality of data types
A method and apparatus for combining multiple image data files of differing sizes, resolutions, and formats in real time into a single data stream for conversion...
US-5,301,302 Memory mapping and special write detection in a system and method for simulating a CPU processor
The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor...
US-5,301,272 Method and apparatus for address space aliasing to identify pixel types
A CPU or other graphics processor provides a pixel data stream to a graphics controller over a system bus. The pixel data stream includes a graphics controller...
US-5,299,318 Processor with a plurality of microprogrammed units, with anticipated execution indicators and means for...
A data processing system having processors with large instruction sets optimized for the execution of brief instructions. The processor (CPU) comprises a...
US-5,297,260 Processor having a plurality of CPUS with one CPU being normally connected to common bus
A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU...
US-5,295,258 Fault-tolerant computer system with online recovery and reintegration of redundant components
A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory...
US-5,293,603 Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus...
US-5,293,493 Preemption control for central processor with cache
A logic controlled gate is inserted in the arbitration logic of a computer system that supports multiple masters on a data bus. In such a system with arbitration...
US-5,291,604 Transparent system interrupts with automated halt state restart
A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, processor state data at the time of...
US-5,291,479 Modular user programmable telecommunications system with distributed processing
A telecommunications system is provided to connect a plurality of dissimilar types of subscriber telecommunications devices and to provide integrated...
US-5,291,420 Remote management system for photographic equipment
A printer processor, a film processor, and a densitometer are connected to a personal computer via a port controller. To diagnose the operational condition of...
US-5,291,370 Compact data processor having a tilting and sliding display
A data processor composed of: a main body including a CPU, a keyboard provided at the top of the main body, a pair of sliding rails provided at both sides of the...
US-5,291,197 One-chip data processor with built-in A/D converter for automatically repeating A/D conversions without...
A data processing unit according to the present invention has a central processing unit, and an analog-to-digital converter circuit associated with a plurality...
US-5,291,189 Direct memory access apparatus in image processing system and external storage device used therein
A direct memory access apparatus includes a CPU, and data of one byte or more to be transferred is stored in a working RAM of the CPU or an external storage...
US-5,287,438 System and method for drawing antialiased polygons
A system (30) draws antialiased polygons. A CPU (32) is connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a 32-bit...
US-5,283,889 Hardware based interface for mode switching to access memory above one megabyte
A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer....
US-5,283,792 Power up/power down controller and power fail detector for processor
A power fail control system for a CPU (10) and external memory (16) utilizes a controller (18). The controller (18) is operable to detect an early power fail...
US-5,280,621 Personal computer having dedicated processors for peripheral devices interconnected to the CPU by way of a...
A plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor. One processor is dedicated to...
US-5,278,836 Multichannel communication processing system
A multichannel communication processing system having line control apparatus means for analyzing receiving frames and channel-controlling transmitting frames,...
US-5,276,862 Safestore frame implementation in a central processor
In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock...
US-5,276,852 Method and apparatus for controlling a processor bus used by multiple processor components during writeback...
A CPU module has a processor, cache memory, cache controller, and system interface attached to a processor bus. The system interface is attached to a system bus...
US-5,276,849 Apparatus and method for maintaining cache/main memory consistency utilizing a dual port FIFO buffer
An apparatus and method for maintaining cache/main memory consistency in a data processing system including a write-through cache (14). For write operations of...
US-5,276,823 Fault-tolerant computer system with redesignation of peripheral processor
A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory...
US-5,274,834 Transparent system interrupts with integrated extended memory addressing
A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, and processor state data at the time...
US-5,274,789 Multiprocessor system having distributed shared resources and dynamic and selective global data replication
Multiprocessor system having distributed shared resources and dynamical and selective global data replication in which a plurality of processors communicate each...
US-5,274,788 High speed memory access for a data processor
A data processor which includes a central processing unit (CPU) coupled to an address bus for supplying an address to an external memory and a data bus for...
US-5,274,777 Digital data processor executing a conditional instruction within a single machine cycle
In a digital data processor having a CPU, a condition instruction is fetched from memory to an instruction register. A first control circuit responds to...
US-5,274,369 Radio paging receiver consuming less electric power
A radio paging receiver having a primary power source, and outputs boosted by DC--DC converters as its secondary power sources. The radio paging receiver is...
US-5,271,348 Drive arrangement
A drive arrangement comprises an a.c. induction motor (M1) having a rotary output shaft, and a drive control (FIG. 2), by which the speed of rotation of the...
US-5,267,217 Apparatus for and method of detecting shape of solder portion
The surface of a solder portion is specular. Besides, it includes a flat plane, a steep inclined plane and a gentle inclined plane. Accordingly, when light is...
US-5,265,240 Channel measurement method and means
Provides a method for measuring the busy utilization time for I/O channel used by any of plural operating systems (OSs) in a CEC. The measured utilization time...
US-5,257,357 Method and apparatus for implementing a priority adjustment of an interrupt in a data processor
An interrupt mechanism allows an interrupt request signal to be adjusted to any priority level specified by the user and provides to a CPU an encoded interrupt...
US-5,257,354 System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of...
A system whereby a central processor continues operation beyond a serialization point before the architecture defines that it is permissible to do so. According...
US-5,253,141 Modular mainframe computer system having an interconnection portion in assembly with a CPU and extending from a...
A modular mainframe computer system having functional units separately housed in respective cabinets aligned in at least one row to form one central unit, the...
US-5,251,320 Power controller for permitting multiple processors to power up shared input/output devices and inhibit power...
A shared power controller for a rack of interface devices which are shared among a plurality of processor units. The shared power controller may be commanded...
US-5,247,673 Multiprocessor system having distributed shared resources and dynamic global data replication
A multiprocessor system has distributed shared resources and dynamic global data replication in which a plurality of processors communicate each with the other...
US-5,247,521 Data processor
In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the...
US-5,243,705 System for rapid return of exceptional processing during sequence operation instruction execution
A high-speed data processor capable of processing a special operation instruction such as a sequence operation instruction which is different from a normal...
US-5,241,640 Disk unit with processors which detect cache status and control port selection for optimizing utilization of...
A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU,...
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