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Patent # Description
US-5,291,420 Remote management system for photographic equipment
A printer processor, a film processor, and a densitometer are connected to a personal computer via a port controller. To diagnose the operational condition of...
US-5,291,370 Compact data processor having a tilting and sliding display
A data processor composed of: a main body including a CPU, a keyboard provided at the top of the main body, a pair of sliding rails provided at both sides of the...
US-5,291,197 One-chip data processor with built-in A/D converter for automatically repeating A/D conversions without...
A data processing unit according to the present invention has a central processing unit, and an analog-to-digital converter circuit associated with a plurality...
US-5,291,189 Direct memory access apparatus in image processing system and external storage device used therein
A direct memory access apparatus includes a CPU, and data of one byte or more to be transferred is stored in a working RAM of the CPU or an external storage...
US-5,287,438 System and method for drawing antialiased polygons
A system (30) draws antialiased polygons. A CPU (32) is connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a 32-bit...
US-5,283,889 Hardware based interface for mode switching to access memory above one megabyte
A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer....
US-5,283,792 Power up/power down controller and power fail detector for processor
A power fail control system for a CPU (10) and external memory (16) utilizes a controller (18). The controller (18) is operable to detect an early power fail...
US-5,280,621 Personal computer having dedicated processors for peripheral devices interconnected to the CPU by way of a...
A plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor. One processor is dedicated to...
US-5,278,836 Multichannel communication processing system
A multichannel communication processing system having line control apparatus means for analyzing receiving frames and channel-controlling transmitting frames,...
US-5,276,862 Safestore frame implementation in a central processor
In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock...
US-5,276,852 Method and apparatus for controlling a processor bus used by multiple processor components during writeback...
A CPU module has a processor, cache memory, cache controller, and system interface attached to a processor bus. The system interface is attached to a system bus...
US-5,276,849 Apparatus and method for maintaining cache/main memory consistency utilizing a dual port FIFO buffer
An apparatus and method for maintaining cache/main memory consistency in a data processing system including a write-through cache (14). For write operations of...
US-5,276,823 Fault-tolerant computer system with redesignation of peripheral processor
A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory...
US-5,274,834 Transparent system interrupts with integrated extended memory addressing
A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, and processor state data at the time...
US-5,274,789 Multiprocessor system having distributed shared resources and dynamic and selective global data replication
Multiprocessor system having distributed shared resources and dynamical and selective global data replication in which a plurality of processors communicate each...
US-5,274,788 High speed memory access for a data processor
A data processor which includes a central processing unit (CPU) coupled to an address bus for supplying an address to an external memory and a data bus for...
US-5,274,777 Digital data processor executing a conditional instruction within a single machine cycle
In a digital data processor having a CPU, a condition instruction is fetched from memory to an instruction register. A first control circuit responds to...
US-5,274,369 Radio paging receiver consuming less electric power
A radio paging receiver having a primary power source, and outputs boosted by DC--DC converters as its secondary power sources. The radio paging receiver is...
US-5,271,348 Drive arrangement
A drive arrangement comprises an a.c. induction motor (M1) having a rotary output shaft, and a drive control (FIG. 2), by which the speed of rotation of the...
US-5,267,217 Apparatus for and method of detecting shape of solder portion
The surface of a solder portion is specular. Besides, it includes a flat plane, a steep inclined plane and a gentle inclined plane. Accordingly, when light is...
US-5,265,240 Channel measurement method and means
Provides a method for measuring the busy utilization time for I/O channel used by any of plural operating systems (OSs) in a CEC. The measured utilization time...
US-5,257,357 Method and apparatus for implementing a priority adjustment of an interrupt in a data processor
An interrupt mechanism allows an interrupt request signal to be adjusted to any priority level specified by the user and provides to a CPU an encoded interrupt...
US-5,257,354 System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of...
A system whereby a central processor continues operation beyond a serialization point before the architecture defines that it is permissible to do so. According...
US-5,253,141 Modular mainframe computer system having an interconnection portion in assembly with a CPU and extending from a...
A modular mainframe computer system having functional units separately housed in respective cabinets aligned in at least one row to form one central unit, the...
US-5,251,320 Power controller for permitting multiple processors to power up shared input/output devices and inhibit power...
A shared power controller for a rack of interface devices which are shared among a plurality of processor units. The shared power controller may be commanded...
US-5,247,673 Multiprocessor system having distributed shared resources and dynamic global data replication
A multiprocessor system has distributed shared resources and dynamic global data replication in which a plurality of processors communicate each with the other...
US-5,247,521 Data processor
In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the...
US-5,243,705 System for rapid return of exceptional processing during sequence operation instruction execution
A high-speed data processor capable of processing a special operation instruction such as a sequence operation instruction which is different from a normal...
US-5,241,640 Disk unit with processors which detect cache status and control port selection for optimizing utilization of...
A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU,...
US-5,241,129 Electronic musical instrument having physical model tone generator
An object of the present invention is to provide an electronic musical instrument which can generate a plurality of tones in spite of the inexpensive and simple...
US-5,237,673 Memory management method for coupled memory multiprocessor systems
A method of managing the memory of a CM multiprocessor computer system is disclosed. A CM multiprocessor computer system includes: a plurality of CPU modules 11a...
US-5,237,658 Linear and orthogonal expansion of array storage in multiprocessor computing systems
A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of...
US-5,231,640 Fault tolerant processor/memory architecture
A primary processor provides control, address and data signals to a shadow comparison ASIC which also receives corresponding signals from a shadow processor...
US-5,228,134 Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface...
US-5,220,348 Electronic drive circuit for multi-laser thermal printer
There is disclosed an automatically adjustable electronic drive circuit for a multi-laser thermal-printer to insure uniformity in printing by all of the lasers....
US-5,218,678 System and method for atomic access to an input/output device with direct memory access
A system (30) for atomic access to an I/O device with DMA includes a CPU (32) connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is...
US-5,218,564 Layout efficient 32-bit shifter/register with 16-bit interface
An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient...
US-5,214,776 Multiprocessor system having global data replication
A multiprocessor system having global data replicated in all local memories, each local memory related to one of the system central processing units (CPUs),...
US-5,214,652 Alternate processor continuation of task of failed processor
Completes on a another CPU the execution of a program, or program task, terminated by a processor error on a first CPU without re-executing any ...
US-5,212,775 Method and apparatus for observing internal memory-mapped registers
A method and apparatus for observing the contents on internal memory-mapped registers of controllers and co-processors which have been integrated on-chip with a...
US-5,210,870 Database sort and merge apparatus with multiple memory arrays having alternating access
A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing:...
US-5,210,858 Clock division chip for computer system which interfaces a slower cache memory controller to be used with a...
A clocking control circuit for a computer system and method for receiving a microprocessor clock signal which drives a microprocessor and for supplying a support...
US-5,206,935 Apparatus and method for fast I/O data transfer in an intelligent cell
A specialized apparatus and method for providing fast programmed I/O for transferring information in a multi-processor environment which includes a CPU, and a...
US-5,204,949 Multi-channel/multi-circuit communication controller
An ISDN communication controller or a multi-circuit communication controller is implemented in a sheet of communication adapter board. For each channel or...
US-5,193,175 Fault-tolerant computer with three independently clocked processors asynchronously executing identical code...
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory...
US-5,193,166 Cache-memory architecture comprising a single address tag for each cache memory
A cache-memory system comprising a processor bus for communicating between an associated processor (CPU) and associated cache-memory management units (CMMUs)...
US-5,193,149 Dual-path computer interconnect system with four-ported packet memory control
A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links provide simultaneous dual paths...
US-5,187,799 Arithmetic-stack processor which precalculates external stack address before needed by CPU for building high...
This is a 32-bit combined arithmetic unit and stack processor (designated as the ASP chip) designed to be a simple, flexible, yet powerful building block for a...
US-5,187,780 Dual-path computer interconnect system with zone manager for packet memory
A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links provide simultaneous dual paths...
US-5,185,875 Method and apparatus for reducing memory read latency in a shared memory system with multiple processors
Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a...
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