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Searching: cpu processor





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Patent # Description
US-5,185,871 Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions
The disclosure describes means for allowing the sequencing of operand fetches to deviate from the conceptual sequence specified in the program. Allowing fetch...
US-5,185,859 Graphics processor, a graphics computer system, and a process of masking selected bits
A graphics processor device performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to external or internal...
US-5,185,745 Scan path diagnostic method
A method of diagnosing memory and CPU boards by using scan rings which are composed of interconnected shift registers. A maintenance processor (MP) down-loads...
US-5,170,481 Microprocessor hold and lock circuitry
A logic circit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request...
US-5,170,473 Communication command control system between CPUs
A communication command control system among a plurality of CPUs includes a control apparatus for transmitting an acknowledge signal to a request signal and...
US-5,168,566 Multi-task control device for central processor task execution control provided as a peripheral device and...
A computer peripheral device incorporating a multi-task control device which is extremely useful for such programs controlling the microcomputer system. In...
US-5,167,023 Translating a dynamic transfer control instruction address in a simulated CPU processor
The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor...
US-5,166,977 Protocol converter for a secure FAX transmission system
A secure facsimile interface includes a main CPU (30) having associated therewith a bulk memory (32) for storing transfer data between a Group 3 facsimile...
US-5,165,023 Parallel processing system with processor array and network communications system for transmitting messages of...
A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are...
US-5,163,145 Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory...
A computer system provides a RESET-signal for resetting registers upon start-up of the system, and includes a central processor unit (CPU) of an optional type...
US-5,157,781 Data processor test architecture
A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register...
US-5,155,843 Error transition mode for multi-processor system
A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of...
US-5,146,589 Refresh control for dynamic memory in multiple processor system
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory...
US-5,142,675 Monitor channel system in use with a recording apparatus
A monitor control system comprises an interrupt processor for executing regular monitor processing by a periodic interrupt occurring at a predetermined time...
US-5,142,536 Data processor
In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the...
US-5,140,564 Exam timer
A timing device for pacing an examinee through a timed, multi-question examination. The device includes means for inputting a plurality of signals corresponding...
US-5,138,708 Digital processor using current state comparison for providing fault tolerance
A highly fault-tolerant processor is comprised of first and second central processing units (CPU) executing the same instruction sequence. Each CPU provides a...
US-5,136,516 Analog and digital speed display device
An analog and digital display device for use with railroad vehicles which comprises: a host processor which transmits operational data received from a digital...
US-5,135,224 Pattern matching game machine of prepaid card system
A pattern matching game machine of a prepaid card system including a plurality of pattern display units mounted on a shaft and arranged in parallel to one...
US-5,133,061 Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of...
An electronic computer system including a central processor and a hierarchical memory system having a large relatively low speed random access system memory and...
US-5,132,971 In-circuit emulator
An in-circuit emulator is inserted in a CPU socket of a target system that uses a program designed to use virtual addresses. The in-circuit emulator includes a...
US-5,129,064 System and method for simulating the I/O of a processing system
The system and method of this invention allows a simulated processor to receive an interrupt request from I/O devices. A simulated interrupt controller routine...
US-5,125,088 Computer system speed control at continuous processor speed
A personal computer is disclosed having a high speed microprocessor which executes in a variety of selectable speed modes to provide greater compatibility with...
US-5,125,084 Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and...
Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of...
US-5,123,094 Interprocessor communications includes second CPU designating memory locations assigned to first CPU and...
A method for performing inter-processor communications in a multiprocessor system combines the sending of a message with the sending of a message interrupt....
US-5,119,494 Application address display window mapper for a sharable MS-DOS processor
In accordance with the present invention, an address mapper is provided between the CPU running a MS-DOS application program and a frame buffer, so as to allow...
US-5,113,500 Multiple cooperating and concurrently operating processors using individually dedicated memories
A personal computer (PC) desktop workstation using a first operating system is enhanced with a single PC bus extension card (SCAMP Board) within its base housing...
US-5,099,516 Digital computer code word identification system
A digital computer system has a central processor unit (CPU). A computer program, entered into the digital computer system for execution thereof, has a program...
US-5,097,470 Diagnostic system for programmable controller with serial data link
A diagnostic system coupled to a programmable logic controller (PLC) via a serial data link monitors the operation of apparatus under the control of the PLC....
US-5,097,409 Multi-processor system with cache memories
A system having a CPU, a main memory and a bus. A cache memory couples the CPU to the bus and is provided with circuitry to indicate the status of a data unit...
US-5,095,520 Method and apparatus for drawing wide lines in a raster graphics system
A method and apparatus for drawing wide lines in a raster graphics system such as a laser printing or display system utilizes a graphics processor with rectangle...
US-5,088,033 Data processing system emulation in a window with a coprocessor and I/O emulation
An emulating data processor includes a host system and an emulating processor with outputs to and inputs from the host system. The emulating processor executes...
US-5,084,814 Data processor with development support features
A data processor with development support features includes an alternate mode of operation in which instructions are received by means of an ...
US-5,081,701 System for controlling data transfer using transfer handshake protocol using transfer complete and transfer...
A circuit for controlling data transfer handshake protocol so that certain protocol events may occur prior to or simultaneously with the completion of a...
US-5,072,376 Measuring utilization of processor shared by multiple system control programs
In a computer system wherein control of a processor is time multiplexed among more than one system control program, the utilization by a system control program...
US-5,072,294 Method and apparatus for analyzing a body having a marker located thereon
A video motion analysis system wherein a camera converts an image of a body having illuminated markers placed thereon into a plurality of image frames. Each...
US-5,056,041 Data processing apparatus with improved bit masking capability
A graphics processor device is disclosed which performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to...
US-5,051,992 Data link control method and system for integrated services digital network
There is a communication system comprising: an integrated services digital network (ISDN) having a plurality of information channels (Bch) and at least one...
US-5,045,997 Data processor
The efficiency of a processor in which a packet is stored in a receiver buffer, processed in a central processing unit, and sent out via a transmitter buffer, is...
US-5,041,962 Computer system with means for regulating effective processing rates
A digital computer system having a local cache memory and a system bus also has a subsystem for regulating the effective processing rate of the central processor...
US-5,034,877 Motion control
A motion and position control for use in a system that includes a motor or other prime mover for moving a tool or other device and a sensor that generates a...
US-5,020,020 Computer interconnect system with transmit-abort function
A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links may provide simultaneous dual...
US-5,008,949 Image processing system
An image processing system has a computer bus line to which a communication controller or the like is connected, an image processor, an RP adapter including a...
US-5,005,121 Integrated CPU and DMA with shared executing unit
A data processor controller for a microprogramming system is constructed with a single operation execution unit serving both a microprocessor and a peripheral...
US-5,003,464 Methods and apparatus for efficient resource allocation
A multiprocessor data processing system is described in which the function of coordinating the actions of all of the processors of the multiprocessor system can...
US-5,001,662 Method and apparatus for multi-gauge computation
Methods and apparatus are provided for performing multi-gauge arithmetic operations in a microprocessor CPU. Special purpose instructions facilitate parallel...
US-5,001,625 Bus structure for overlapped data transfer
An improved system bus structure for versatile use in various digital computer architecture configurations, particularly those of mini-supercomputers, and,...
US-4,996,639 Data processor including an A/D converter for converting a plurality of analog input channels into digital data
A data processor includes a CPU and an A/D converter for converting one of several analog inputs into digital data. A data memory stores data designating analog...
US-4,989,208 Data processor
In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the...
US-4,987,534 Processor having synchronized operation between a CPU and a vector processor
A vector processor which maintains synchronization with an associated CPU by limiting the operational instruction proceedings. The vector processor utilizes an...
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