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Searching: cpu processor





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Patent # Description
US-5,265,240 Channel measurement method and means
Provides a method for measuring the busy utilization time for I/O channel used by any of plural operating systems (OSs) in a CEC. The measured utilization time...
US-5,257,357 Method and apparatus for implementing a priority adjustment of an interrupt in a data processor
An interrupt mechanism allows an interrupt request signal to be adjusted to any priority level specified by the user and provides to a CPU an encoded interrupt...
US-5,257,354 System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of...
A system whereby a central processor continues operation beyond a serialization point before the architecture defines that it is permissible to do so. According...
US-5,253,141 Modular mainframe computer system having an interconnection portion in assembly with a CPU and extending from a...
A modular mainframe computer system having functional units separately housed in respective cabinets aligned in at least one row to form one central unit, the...
US-5,251,320 Power controller for permitting multiple processors to power up shared input/output devices and inhibit power...
A shared power controller for a rack of interface devices which are shared among a plurality of processor units. The shared power controller may be commanded...
US-5,247,673 Multiprocessor system having distributed shared resources and dynamic global data replication
A multiprocessor system has distributed shared resources and dynamic global data replication in which a plurality of processors communicate each with the other...
US-5,247,521 Data processor
In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the...
US-5,243,705 System for rapid return of exceptional processing during sequence operation instruction execution
A high-speed data processor capable of processing a special operation instruction such as a sequence operation instruction which is different from a normal...
US-5,241,640 Disk unit with processors which detect cache status and control port selection for optimizing utilization of...
A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU,...
US-5,241,129 Electronic musical instrument having physical model tone generator
An object of the present invention is to provide an electronic musical instrument which can generate a plurality of tones in spite of the inexpensive and simple...
US-5,237,673 Memory management method for coupled memory multiprocessor systems
A method of managing the memory of a CM multiprocessor computer system is disclosed. A CM multiprocessor computer system includes: a plurality of CPU modules 11a...
US-5,237,658 Linear and orthogonal expansion of array storage in multiprocessor computing systems
A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of...
US-5,231,640 Fault tolerant processor/memory architecture
A primary processor provides control, address and data signals to a shadow comparison ASIC which also receives corresponding signals from a shadow processor...
US-5,228,134 Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface...
US-5,220,348 Electronic drive circuit for multi-laser thermal printer
There is disclosed an automatically adjustable electronic drive circuit for a multi-laser thermal-printer to insure uniformity in printing by all of the lasers....
US-5,218,678 System and method for atomic access to an input/output device with direct memory access
A system (30) for atomic access to an I/O device with DMA includes a CPU (32) connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is...
US-5,218,564 Layout efficient 32-bit shifter/register with 16-bit interface
An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient...
US-5,214,776 Multiprocessor system having global data replication
A multiprocessor system having global data replicated in all local memories, each local memory related to one of the system central processing units (CPUs),...
US-5,214,652 Alternate processor continuation of task of failed processor
Completes on a another CPU the execution of a program, or program task, terminated by a processor error on a first CPU without re-executing any ...
US-5,212,775 Method and apparatus for observing internal memory-mapped registers
A method and apparatus for observing the contents on internal memory-mapped registers of controllers and co-processors which have been integrated on-chip with a...
US-5,210,870 Database sort and merge apparatus with multiple memory arrays having alternating access
A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing:...
US-5,210,858 Clock division chip for computer system which interfaces a slower cache memory controller to be used with a...
A clocking control circuit for a computer system and method for receiving a microprocessor clock signal which drives a microprocessor and for supplying a support...
US-5,206,935 Apparatus and method for fast I/O data transfer in an intelligent cell
A specialized apparatus and method for providing fast programmed I/O for transferring information in a multi-processor environment which includes a CPU, and a...
US-5,204,949 Multi-channel/multi-circuit communication controller
An ISDN communication controller or a multi-circuit communication controller is implemented in a sheet of communication adapter board. For each channel or...
US-5,193,175 Fault-tolerant computer with three independently clocked processors asynchronously executing identical code...
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory...
US-5,193,166 Cache-memory architecture comprising a single address tag for each cache memory
A cache-memory system comprising a processor bus for communicating between an associated processor (CPU) and associated cache-memory management units (CMMUs)...
US-5,193,149 Dual-path computer interconnect system with four-ported packet memory control
A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links provide simultaneous dual paths...
US-5,187,799 Arithmetic-stack processor which precalculates external stack address before needed by CPU for building high...
This is a 32-bit combined arithmetic unit and stack processor (designated as the ASP chip) designed to be a simple, flexible, yet powerful building block for a...
US-5,187,780 Dual-path computer interconnect system with zone manager for packet memory
A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links provide simultaneous dual paths...
US-5,185,875 Method and apparatus for reducing memory read latency in a shared memory system with multiple processors
Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a...
US-5,185,871 Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions
The disclosure describes means for allowing the sequencing of operand fetches to deviate from the conceptual sequence specified in the program. Allowing fetch...
US-5,185,859 Graphics processor, a graphics computer system, and a process of masking selected bits
A graphics processor device performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to external or internal...
US-5,185,745 Scan path diagnostic method
A method of diagnosing memory and CPU boards by using scan rings which are composed of interconnected shift registers. A maintenance processor (MP) down-loads...
US-5,170,481 Microprocessor hold and lock circuitry
A logic circit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request...
US-5,170,473 Communication command control system between CPUs
A communication command control system among a plurality of CPUs includes a control apparatus for transmitting an acknowledge signal to a request signal and...
US-5,168,566 Multi-task control device for central processor task execution control provided as a peripheral device and...
A computer peripheral device incorporating a multi-task control device which is extremely useful for such programs controlling the microcomputer system. In...
US-5,167,023 Translating a dynamic transfer control instruction address in a simulated CPU processor
The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor...
US-5,166,977 Protocol converter for a secure FAX transmission system
A secure facsimile interface includes a main CPU (30) having associated therewith a bulk memory (32) for storing transfer data between a Group 3 facsimile...
US-5,165,023 Parallel processing system with processor array and network communications system for transmitting messages of...
A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are...
US-5,163,145 Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory...
A computer system provides a RESET-signal for resetting registers upon start-up of the system, and includes a central processor unit (CPU) of an optional type...
US-5,157,781 Data processor test architecture
A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register...
US-5,155,843 Error transition mode for multi-processor system
A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of...
US-5,146,589 Refresh control for dynamic memory in multiple processor system
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory...
US-5,142,675 Monitor channel system in use with a recording apparatus
A monitor control system comprises an interrupt processor for executing regular monitor processing by a periodic interrupt occurring at a predetermined time...
US-5,142,536 Data processor
In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the...
US-5,140,564 Exam timer
A timing device for pacing an examinee through a timed, multi-question examination. The device includes means for inputting a plurality of signals corresponding...
US-5,138,708 Digital processor using current state comparison for providing fault tolerance
A highly fault-tolerant processor is comprised of first and second central processing units (CPU) executing the same instruction sequence. Each CPU provides a...
US-5,136,516 Analog and digital speed display device
An analog and digital display device for use with railroad vehicles which comprises: a host processor which transmits operational data received from a digital...
US-5,135,224 Pattern matching game machine of prepaid card system
A pattern matching game machine of a prepaid card system including a plurality of pattern display units mounted on a shaft and arranged in parallel to one...
US-5,133,061 Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of...
An electronic computer system including a central processor and a hierarchical memory system having a large relatively low speed random access system memory and...
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