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Patent # Description
US-8,898,429 Application processor and a computing system having the same
An application processor includes a system memory unit, peripheral devices, a control unit and a central processing unit (CPU). The system memory unit includes...
US-8,898,172 Parallel generation of topics from documents
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for enhanced parallel latent Dirichlet allocation (PLDA+). A...
US-8,893,143 Hardware virtualization for media processing
Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of...
US-8,893,103 Automatic asynchronous offload to many-core coprocessors
Methods and systems for asynchronous offload to many-core coprocessors include splitting a loop in an input source code into a sampling sub-part, a many...
US-8,892,803 Interrupt on/off management apparatus and method for multi-core processor
Provided are an interrupt on/off management apparatus and method for a multi-core processor having a plurality of central processing unit (CPU) cores. The...
US-8,885,180 Portable handheld device with multi-core image processor
A portable handheld device includes an image sensor for capturing an image; an orientation sensor for determining a rotation of the image sensor; and a...
US-8,885,179 Portable handheld device with multi-core image processor
According to an aspect of the disclosure, a portable handheld device includes a CPU for processing a script; a multi-core processor for processing an image, and...
US-8,880,789 Optimal power usage in decoding a content stream stored in a secondary storage
Decoding a content of interest with optimal power usage. In an embodiment, a central processing unit (CPU) retrieves the frames of a data stream of interest...
US-8,873,747 Key management using security enclave processor
An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the...
US-8,869,176 Exposing host operating system services to an auxillary processor
Aspect methods, systems and devices may be configured to perform two-way and/or reverse procedure calls in a computing device or across a network to offload the...
US-8,868,947 Fan control for determining a fan speed that is closer to an optimal fan speed based on an amount of measured...
In general, in one aspect, the disclosure describes running a cooling fan within a computer at low speed while the computer is in low temperature operations...
US-8,868,848 Sharing virtual memory-based multi-version data between the heterogenous processors of a computer platform
A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors...
US-8,862,831 Method and apparatus to facilitate shared pointers in a heterogeneous platform
A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous...
US-8,861,013 Image forming apparatus
A CPU perform the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except...
US-8,860,741 Graphics processor with memory management unit and cache coherent link
In contrast to a conventional computing system in which the graphics processor (graphics processing unit or GPU) is treated as a slave to one or several CPUs,...
US-8,856,504 Secure virtual machine bootstrap in untrusted cloud infrastructures
Techniques are described for securely booting and executing a virtual machine (VM) image in an untrusted cloud infrastructure. A multi-core processor may be...
US-8,856,379 Intelligent network interface system and method for protocol processing
A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with...
US-8,856,196 System and method for transferring tasks in a multi-core processor based on trial execution and core node
A multi core system for allocating a task generated from a control system program to an appropriate CPU core and executing the task includes a trial-execution...
US-8,850,262 Inter-processor failure detection and recovery
An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for...
US-8,843,669 Guest partition high CPU usage mitigation when performing data transfers in a guest partition
An invention is disclosed for offloading operations, such data transfers, of a guest partition to a host partition. A guest operating system is presented with...
US-8,838,949 Direct scatter loading of executable software image from a primary processor to one or more secondary processor...
In a multi-processor system, an executable software image including an image header and a segmented data image is scatter loaded from a first processor to a...
US-8,838,940 CPU utilization metering on systems that include multiple hardware threads per core
Indicating usage in a system is disclosed. Indicating includes obtaining active thread information related to a number of hardware threads in a processor core,...
US-8,835,321 Method for forming fine patterns of a semiconductor device
A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region,...
US-8,832,465 Security enclave processor for a system on a chip
An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the...
US-8,830,245 Load balancing between general purpose processors and graphics processors
Disclosed are various embodiments for facilitating load balancing between central processing units (CPUs) and graphics processing units (GPUs). A request is...
US-8,826,270 Regulating memory bandwidth via CPU scheduling
Technologies are described herein for regulating memory bandwidth usage in virtual machines via CPU scheduling. A virtual machine monitor ("VMM") executing on a...
US-8,825,926 Processor with assignable general purpose register set
A processor has a central processing unit (CPU), a first CPU register set, a second CPU register set, a multiplexer logic for either coupling the first or the...
US-8,819,320 Executing an instruction for performing a configuration virtual topology change
In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest...
US-8,819,225 Hardware-assisted integrity monitor
A hardware-assisted integrity monitor may include one or more target machines and/or monitor machines. A target machine may include one or more processors,...
US-8,811,470 Integrated circuit for video/audio processing
An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of...
US-8,811,386 Packet handler for high speed data networks
An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal...
US-8,806,215 Method and system for robust watermark insertion and extraction for digital set-top boxes
Methods and systems for robust watermark insertion and extraction for digital set-top boxes are disclosed and may include descrambling, detecting watermarking...
US-8,805,948 Intelligent network interface system and method for protocol processing
A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with...
US-8,799,687 Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state...
A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the...
US-8,799,547 Data packet processing method for a multi core processor
A method for processing a data packet in a network server system comprising at least one central processor unit (CPU) having a plurality of cores; and a network...
US-8,789,063 Master and subordinate operating system kernels for heterogeneous multiprocessor systems
Systems and methods establish communication and control between various heterogeneous processors in a computing system so that an operating system can run an...
US-8,787,632 Apparatus and method for reducing noise in fingerprint sensing circuits
An apparatus for reducing noise in fingerprint sensing circuits is disclosed in one embodiment of the invention as including a fingerprint sensing area onto...
US-8,782,291 Notebook having secondary processor coupled by a multiplexer to a content source or disk drive
In some embodiments, a notebook including a content source (e.g., a DVD or other display data source), mass storage device (e.g., hard disk drive), auxiliary...
US-8,782,199 Parsing a packet header
An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a...
US-8,781,748 System and method for generating images of subsurface structures
A system and method for generating images of a subsurface region of interest is provided. In one embodiment, a computer-implemented method of generating images...
US-8,776,079 Task processor
A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage...
US-8,776,035 Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores
A compiler may optimize source code and any referenced libraries to execute on a plurality of different processor architecture implementations. For example, if...
US-8,776,030 Partitioning CUDA code for execution by a general purpose processor
One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on...
US-8,775,757 Trust zone support in system on a chip having security enclave processor
An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the...
US-8,769,534 Measuring CPU utilization in a cloud computing infrastructure by artificially executing a bursting application...
Novel techniques are provided to determine concurrent hardware resource usage as expressed in activity performed by hardware processors. A cloud computing...
US-8,769,508 Virtual machine hardware for RISC and CISC processors
A hardware Java.TM. accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to...
US-8,762,366 Executing database queries using multiple processors
A system and a method are disclosed for efficiently executing database queries using a computing device that includes a central processing unit (CPU) and a...
US-8,761,553 Optical network structures for multi-core central processor unit
Provided is an optical network structure. To configure an optical network structure between hundreds or more of cores in a CPU, intersection between waveguides...
US-8,760,452 Integrated graphics processor data copy elimination method and apparatus when using system memory
A method and apparatus for processing data in a system comprising a central processing unit (CPU), a system memory, and a graphics processing unit (GPU)...
US-8,756,406 Method and apparatus for programmable coupling between CPU and co-processor
In one embodiment the present invention includes a method and apparatus for enabling a main core and one or more co-processors to operate in a de-coupled mode,...
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