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United States Patent Application 20160217845
Kind Code A1
NAKAMINATO; Tsutomu ;   et al. July 28, 2016

INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD

Abstract

An information processing apparatus includes a memory that is volatile, a memory controller connected to the memory in an information exchangeable manner, and a clock enable (CKE) controller. The CKE controller controls a CKE signal in response to a request for a proxy in self-refresh control, the CKE signal being transmitted from the memory controller to the memory and being controlled to be kept low until cancellation of the proxy is requested. At a time of shifting to a power-saving mode, the memory controller stores information held by a central processing unit (CPU) in the memory and causes the memory to shift to a self-refresh mode. At a time of recovery from the power-saving mode, the memory controller requests the CKE controller for the cancellation of the proxy in the self-refresh control and thereafter cancels the self-refresh mode of the memory.


Inventors: NAKAMINATO; Tsutomu; (Kanagawa, JP) ; TERUI; Yoshinobu; (Kanagawa, JP) ; KANEKO; Tomokazu; (Kanagawa, JP) ; NAKAMOTO; Katsuma; (Kanagawa, JP) ; TERUI; Yoshitaka; (Kanagawa, JP) ; SHIOYASU; Asahito; (Kanagawa, JP)
Applicant:
Name City State Country Type

FUJI XEROX CO., LTD.

Tokyo

JP
Assignee: FUJI XEROX CO., LTD.
Tokyo
JP

Family ID: 1000002000239
Appl. No.: 14/810620
Filed: July 28, 2015


Current U.S. Class: 1/1
Current CPC Class: G11C 11/4076 20130101; G11C 11/4074 20130101; G11C 11/40615 20130101
International Class: G11C 11/4076 20060101 G11C011/4076; G11C 11/4074 20060101 G11C011/4074; G11C 11/406 20060101 G11C011/406

Foreign Application Data

DateCodeApplication Number
Jan 22, 2015JP2015-010579

Claims



1. An information processing apparatus comprising: a memory that is volatile; a memory controller connected to the memory in an information exchangeable manner; and a clock enable (CKE) controller that controls a CKE signal in response to a request for a proxy in self-refresh control, the CKE signal being transmitted from the memory controller to the memory and being controlled to be kept low until cancellation of the proxy is requested, wherein at a time of shifting to a power-saving mode, the memory controller stores information held by a central processing unit (CPU) in the memory and causes the memory to shift to a self-refresh mode, and at a time of recovery from the power-saving mode, the memory controller requests the CKE controller for the cancellation of the proxy in the self-refresh control and thereafter cancels the self-refresh mode of the memory.

2. The information processing apparatus according to claim 1, wherein before the memory controller requests the CKE controller for the cancellation of the proxy in the self-refresh control at the time of recovery from the power-saving mode, the memory controller transmits a command for initializing the memory and a command for causing the memory to shift to a self-refresh mode.

3. An information processing method comprising: controlling a CKE signal in response to a request for a proxy in self-refresh control, the CKE signal being transmitted to a memory that is volatile from a memory controller connected to the memory in an information exchangeable manner, the CKE signal being controlled to be kept low until cancellation of the proxy is requested, wherein at a time of shifting to a power-saving mode, information held by a CPU is stored in the memory, and the memory is caused to shift to a self-refresh mode, and at a time of recovery from the power-saving mode, the cancellation of the proxy in the self-refresh control is requested, and thereafter the self-refresh mode of the memory is cancelled.
Description



CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2015-010579 filed Jan. 22, 2015.

BACKGROUND

Technical Field

[0002] The present invention relates to an information processing apparatus and an information processing method.

SUMMARY

[0003] According to an aspect of the invention, there is provided an information processing apparatus including a memory that is volatile, a memory controller connected to the memory in an information exchangeable manner, and a clock enable (CKE) controller. The CKE controller controls a CKE signal in response to a request for a proxy in self-refresh control, the CKE signal being transmitted from the memory controller to the memory and being controlled to be kept low until cancellation of the proxy is requested. At a time of shifting to a power-saving mode, the memory controller stores information held by a central processing unit (CPU) in the memory and causes the memory to shift to a self-refresh mode. At a time of recovery from the power-saving mode, the memory controller requests the CKE controller for the cancellation of the proxy in the self-refresh control and thereafter cancels the self-refresh mode of the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Exemplary embodiments of the present invention will be described in detail based on the following figures, wherein:

[0005] FIG. 1 is a block diagram illustrating a configuration example of an information processing apparatus according to an exemplary embodiment;

[0006] FIG. 2 is a flowchart illustrating how the information processing apparatus operates after power-on and at the time of shifting to a power-saving mode; and

[0007] FIG. 3 is a flowchart illustrating how the information processing apparatus operates to recover from a power-saving mode.

DETAILED DESCRIPTION

[0008] Exemplary Embodiment

Configuration of Information Processing Apparatus

[0009] FIG. 1 is a block diagram illustrating a configuration example of an information processing apparatus according to an exemplary embodiment.

[0010] An information processing apparatus 1 includes a central processing unit (CPU) 2, a clock enable (CKE) controller 3, a register 4, a dynamic random access memory (DRAM) 5, a logic circuit 6, power supply circuits 70 and 71, an application specific integrated circuit (ASIC) 80, an interface (I/F) 81, and a user interface (UI) 90.

[0011] The CPU 2 includes a DRAM controller 20. The CPU 2 is connected, in such a manner as to allow data and signals to be exchanged, to the logic circuit 6, to the power supply circuits 70 and 71 via the logic circuit 6 and to the DRAM 5 via the DRAM controller 20. Note that the DRAM controller 20 is connected to the DRAM 5 through a clock (CLK) signal line for clock signal transmission, a CKE signal line for CKE signal transmission, and a dedicated bus for data transmission and reception in a data exchangeable manner. The CPU 2 controls the entire information processing apparatus 1.

[0012] The CKE controller 3 is disposed on the CKE signal line between the DRAM controller 20 and the DRAM 5. The CKE controller 3 controls transmission of a CKE signal from the DRAM controller 20 to the DRAM 5 in such a manner as to either allow the CKE signal to pass through the CKE controller 3 to the DRAM 5 or keep the CKE signal to be transmitted to the DRAM 5 at a low level regardless of the level of the CKE signal transmitted from the DRAM controller 20. While the CKE signal is being kept at the low level, a self-refresh operation in which refreshing is automatically performed in the memory is continued in the DRAM 5. When the CKE signal is switched to a high level, the self-refresh mode is cancelled, and refreshing is performed in the DRAM 5 in accordance with a clock signal transmitted from the DRAM controller 20.

[0013] The register 4 is a circuit for storing information indicating that the CPU 2 is in a power-saving mode. The register 4 is connected to the DRAM controller 20 in a data exchangeable manner.

[0014] The CKE controller 3 and the register 4 are formed as, for example, a complex programmable logic device (CPLD).

[0015] The DRAM 5 is used as a main memory, and data necessary for various processes performed by the CPU 2 is stored in the DRAM 5. The DRAM 5 is a volatile memory, and the mode thereof is switched between a self-refresh mode and a normal operation mode under the control of the DRAM controller 20. In the self-refresh mode, refreshing is automatically performed in the DRAM 5 at appropriate refresh intervals. In the normal operation mode, refreshing is performed under the control of the DRAM controller 20.

[0016] When the DRAM 5 enters the self-refresh mode, refreshing is automatically performed at appropriate refresh intervals in the DRAM 5. A high-level CKE signal corresponds to output of a cancellation signal for cancelling the self-refresh mode. A low-level CKE signal corresponds to output of a self-refresh designation signal for designating shifting to the self-refresh mode.

[0017] A case where a volatile memory used as a main memory is a DRAM will be described in the present exemplary embodiment, but the volatile memory may be a volatile memory of another type.

[0018] The UI 90 is connected to the logic circuit 6 in a signal exchangeable manner and includes a designation button used by a user for designating recovery from the power-saving mode. Further, the logic circuit 6 is connected to the ASIC 80 and the I/F 81 that are controllable for recovery from power-saving mode, and the I/F 81 is provided for exchanging data and signals with an external device through a network.

[0019] The power supply circuit 70 supplies power to units including the CPU 2 and the DRAM controller 20 of the information processing apparatus 1 and is connected to the logic circuit 6 in a signal exchangeable manner. The power supply circuit 70 is controlled by the logic circuit 6 with respect to the power supply to and power disconnection from the units including the CPU 2 and the DRAM controller 20.

[0020] The power supply circuit 71 supplies power to the DRAM 5 and is connected to the logic circuit 6 in a signal exchangeable manner. The power supply circuit 71 is controlled by the logic circuit 6 with respect to the power supply to and power disconnection from the DRAM 5.

Operation of Information Processing Apparatus

[0021] Next, (1) Power-on and Power-saving-mode Shifting Operation and (2) Recovery Operation will be described as effects of the present exemplary embodiment.

(1) Power-on and Power-saving-mode Shifting Operation

[0022] FIG. 2 is a flowchart illustrating how the information processing apparatus 1 operates after power-on and at the time of shifting to a power-saving mode. Note that FIG. 2 illustrates the CPU 2 to represent operations of the CPU 2 and the DRAM controller 20.

[0023] If the CPU 2 determines that the power source of the information processing apparatus 1 is turned on in response to a power supply from the power supply circuit 70 under the control of the logic circuit 6 (S200: YES), the CPU 2 instructs the DRAM controller 20 to transmit a command for initializing the DRAM 5 (S201). The DRAM controller 20 transmits the DRAM initialization command to the DRAM 5 through the dedicated bus.

[0024] Upon receiving the DRAM initialization command (S500), the DRAM 5 performs initialization (S501) and waits for a signal from the CPU 2 (S502).

[0025] After the DRAM 5 is initialized and enters the standby mode, the CPU 2 executes various processes and accesses the DRAM 5 as necessary (S202).

[0026] Meanwhile, the DRAM 5 operates in response to the access by the CPU 2 (S503).

[0027] If the CPU 2 determines that the CPU 2 is to shift to the power-saving mode (S203: YES), the CPU 2 outputs a power-saving designation signal indicating designation of switching to the power-saving mode to the logic circuit 6 and the DRAM controller 20. The CPU 2 also writes information set in the DRAM controller 20 to the DRAM 5. The DRAM controller 20 transmits the self-refresh shift command to the DRAM 5 (S204).

[0028] Note that the CPU 2 determines whether to shift to the power-saving mode on the basis of, for example, an application or input, of the power-saving designation signal indicating switching to the power-saving mode, received from an external device through the UI 90 and the network.

[0029] An operation designated by the self-refresh shift command includes an operation of writing the refresh intervals currently set in the DRAM controller 20 to the DRAM 5 through the dedicated bus.

[0030] The self-refresh shift command is implemented when the DRAM controller 20 asserts a CKE signal (performs control to set the CKE signal at a low level) through the CKE signal line. When receiving the self-refresh shift command (S504), that is, when receiving the CKE signal set at the low level, the DRAM 5 shifts to the self-refresh mode (S505 and 5506) and the self-refresh operation is performed in which refreshing is automatically performed in the DRAM 5.

[0031] After step S204, the CPU 2 requests the CKE controller 3 to act as a proxy in the self-refresh control (S205). The CPU 2 stores information indicating the power-saving mode in the register 4.

[0032] Upon receiving the request for the proxy in the self-refresh control (S300), the CKE controller 3 keeps the CKE signal to be input to the DRAM 5 at the low level (S301). In other words, while being acting as a proxy in the self-refresh control, the CKE controller 3 keeps the CKE signal to be input to the DRAM 5 at the low level even if the CKE signal from the DRAM controller 20 is switched to the high level.

[0033] The power-saving designation signal output from the CPU 2 to the DRAM controller 20 before step 5204 is also output to the logic circuit 6. The logic circuit 6 controls the power supply circuit 70 in such a manner that power supplied by the power supply circuit 70 to the units including the CPU 2 and the DRAM controller 20 is disconnected a predetermined time after the CPU 2 inputs the power-saving designation signal indicating designation of switching to the power-saving mode. As the predetermined time, a time required for the DRAM controller 20 to perform step S205 in FIG. 2 is measured in advance, and the measured time or a time longer than the measured time is used.

[0034] Accordingly, after the DRAM controller 20 performs steps S204 and S206, power supply to the units including the CPU 2 and the DRAM controller 20 of the information processing apparatus 1 is disconnected under the control of the power supply circuit 70 performed by the logic circuit 6 (S206 and S207). In other words, power supply to the units of the information processing apparatus 1 other than the DRAM 5 and the register 4 to which power is supplied by the power supply circuit 71 is disconnected, and the information processing apparatus 1 shifts to the power-saving mode.

(2) Recovery Operation

[0035] Next, an operation of recovery from the power-saving mode will be described.

[0036] FIG. 3 is a flowchart illustrating how the information processing apparatus 1 operates to recover from the power-saving mode. Note that FIG. 3 illustrates the CPU 2 to represent operations of the CPU 2 and the DRAM controller 20.

[0037] When the logic circuit 6 receives a recovery designation signal indicating designation of recovery from the power-saving mode (S208: YES), power is supplied from the power supply circuit 70 to the CPU 2 and the DRAM controller 20 under the control of the power supply circuit 70 performed by the logic circuit 6 (S209). Alternatively, the power may be supplied to the CPU 2 and the DRAM controller 20 when power is supplied to the units of the information processing apparatus 1 in accordance with a user operation of switching on a power switch (not illustrated). Note that the recovery designation signal indicating designation of recovery from the power-saving mode is input in accordance with a user operation of pressing a power-saving recovery designation button (not illustrated) included on the UI 90 or is input from the external device through the network.

[0038] In step 5208, the CPU 2 determines whether information indicating the power-saving mode is stored in the register 4 to thereby determine whether the start of power supply to the CPU 2 and the DRAM controller 20 is attributable to recovery from the power-saving mode or recovery from a state where power supply to the entire information processing apparatus 1 is stopped due to a user operation of switching off the power switch (not illustrated).

[0039] When the power supply is started, the CPU 2 controls the DRAM controller 20 to transmit a DRAM initialization command to the DRAM 5 through the dedicated bus (S210).

[0040] The DRAM controller 20 also transmits the self-refresh shift command to the DRAM 5 (S211).

[0041] Note that since the CKE controller 3 keeps, at the low level, the CKE signal to be input to the DRAM 5 (S302), the DRAM 5 ignores the DRAM initialization command in step 5210 (S507). In addition, since the CKE signal is at the low level at the time of transmitting the self-refresh shift command in step 5211, the low level thereof is consistent with the low level of the CKE signal output by the CKE controller 3 (S508). In other words, the state of the DRAM 5 (self-refresh mode) is consistent with the CKE signal output by the DRAM controller 20.

[0042] Note that the operations in steps 5210 and 5211 are performed by a CPU that does not support an operation performed in response to recovery from the power-saving mode, whereas some CPUs are designed not to perform the operations and thus support the operation performed in response to recovery from the power-saving mode. Even though the operations are not performed, recovery from the power-saving mode may be performed in the present configuration.

[0043] Next, the DRAM controller 20 of the CPU 2 requests the CKE controller 3 to cancel the proxy in the self-refresh control (S212).

[0044] The CKE controller 3 receives the request for cancellation of the proxy in the self-refresh control from the DRAM controller 20 (S303) and causes the CKE signal to be controlled by the CPU 2 (S304). In other words, the CKE controller 3 allows the CKE signal output from the DRAM controller 20 to pass through the CKE controller 3 to the DRAM 5.

[0045] Next, the DRAM controller 20 negates the CKE signal (controls the CKE signal to switch to the high level) to thereby output a cancellation signal for cancelling the self-refresh mode to the DRAM 5 and thus cancels the self-refresh mode of the DRAM 5 (S213). When receiving the CKE signal switched to the high level, the DRAM 5 exits the self-refresh mode (S509) and becomes ready for reading and writing information under the control of the DRAM controller 20 (S510).

[0046] The DRAM controller 20 also clears the register 4.

[0047] When the power supply circuit 70 starts power supply, the CPU 2 acquires data stored in the DRAM 5 through the DRAM controller 20 and performs the operation of recovery from the power-saving mode and other operations (S214 and S511).

[0048] As described above, at the time of shifting to the power-saving mode, the DRAM controller 20 of the information processing apparatus 1 according to the present exemplary embodiment controls the DRAM 5 to cause the DRAM 5 to shift to the self-refresh mode after information set in the DRAM controller 20 is stored in the DRAM 5, and power supply to the DRAM controller 20 is disconnected after the information indicating the power-saving mode is stored in the register 4.

[0049] When power supply to the DRAM controller 20 is started, the DRAM controller 20 initializes the DRAM 5 regardless of whether the start is attributable to recovery from the power-saving mode. The DRAM controller 20 performs the operation of recovery from the power-saving mode on the basis of the information stored in the DRAM 5 after cancelling the self-refresh mode after causing the DRAM 5 to shift to the self-refresh mode, with an initial value of the CKE signal being undefined.

[0050] For the operation of recovery from the power-saving mode, the CKE controller 3 keeps the CKE signal at the low level to ignore the initialization of the DRAM 5 and shifting to the self-refresh mode. Subsequently, the CKE controller 3 allows the CKE signal to pass through the CKE controller 3 to cancel the self-refresh mode of the DRAM 5. The operation of recovery from the power-saving mode is then performed on the basis of the information stored in the DRAM 5. Accordingly, the DRAM 5 is not initialized in the case of recovery from the power-saving mode. This enables even a CPU designed to set a CKE initial value at a low level to reliably use information stored in the DRAM 5 at the time of recovery from the power-saving mode.

[0051] The CPU 2 stores the information indicating a state before shifting to the power-saving mode in the DRAM 5 and reads the information stored in the DRAM 5 at the time of recovery from the power-saving mode. The CPU 2 returns to the state before shifting to the power-saving mode in this manner. Accordingly, at the time of recovery from the power-saving mode, the CPU 2 may return to the state before shifting to the power-saving mode more quickly than in a case where a CPU stores information indicating the state before shifting to the power-saving mode in a non-volatile memory, reads the information from the non-volatile memory at the time of recovery from the power-saving mode, and returns to the state before shifting to the power-saving mode.

Other Exemplary Embodiments

[0052] Note that the exemplary embodiment of the invention is not limited to the aforementioned exemplary embodiment, and various modifications may be made without departing from the scope of the exemplary embodiment of the invention.

[0053] Mutual changes, deletions, additions, and the like of steps described above in the aforementioned exemplary embodiments may be made without departing from the gist of the present invention.

[0054] The foregoing description of the exemplary embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in the art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, thereby enabling others skilled in the art to understand the invention for various embodiments and with the various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.

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