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United States Patent Application 20160291248
Kind Code A1
HuangFu; Yourui October 6, 2016

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Abstract

A semiconductor device and a method for producing a semiconductor device are disclosed. The semiconductor device includes: a first silicon layer; a first dielectric layer, located on the first silicon layer, where the first dielectric layer includes a window, and a bottom horizontal size of the window of the first dielectric layer is not greater than 20 nm; and a III-V semiconductor layer, located on the first dielectric layer and in the window of the first dielectric layer, and connected to the first silicon layer in the window of the first dielectric layer. A III-V semiconductor material of the semiconductor device has no threading dislocations, and therefore has relatively high performance.


Inventors: HuangFu; Yourui; (Hangzhou, CN)
Applicant:
Name City State Country Type

HUAWEI TECHNOLOGIES CO.,LTD.

Shenzhen

CN
Assignee: HUAWEI TECHNOLOGIES CO.,LTD.
Shenzhen
CN

Family ID: 1000002018489
Appl. No.: 15/186681
Filed: June 20, 2016


Related U.S. Patent Documents

Application NumberFiling DatePatent Number
PCT/CN2013/090099Dec 20, 2013
15186681

Current U.S. Class: 1/1
Current CPC Class: G02B 6/122 20130101; G02B 2006/12123 20130101; H01S 5/3013 20130101; H01S 5/026 20130101; H01S 5/323 20130101; H01L 21/308 20130101; H01L 21/31144 20130101; H01L 21/02538 20130101; H01L 21/02636 20130101; H01L 21/0273 20130101; H01L 21/7624 20130101; H01L 29/20 20130101; H01L 31/1035 20130101; H01L 31/02325 20130101; H01L 29/78 20130101; G02B 6/13 20130101; H01S 5/02296 20130101
International Class: G02B 6/122 20060101 G02B006/122; H01S 5/30 20060101 H01S005/30; H01S 5/026 20060101 H01S005/026; H01S 5/323 20060101 H01S005/323; H01L 21/308 20060101 H01L021/308; H01L 21/311 20060101 H01L021/311; H01L 21/02 20060101 H01L021/02; H01L 21/027 20060101 H01L021/027; H01L 21/762 20060101 H01L021/762; H01L 29/20 20060101 H01L029/20; H01L 31/103 20060101 H01L031/103; H01L 31/0232 20060101 H01L031/0232; H01L 29/78 20060101 H01L029/78; G02B 6/13 20060101 G02B006/13; H01S 5/022 20060101 H01S005/022

Claims



1. A method for producing a semiconductor device, comprising: etching a silicon layer of silicon on insulator (SOI) using a patterned template as a mask, wherein the SOI comprises a silicon substrate, a dielectric layer on the silicon substrate, and the silicon layer on the dielectric layer, and wherein a window of the silicon layer is etched to expose the dielectric layer; etching the dielectric layer using the silicon layer having the window as a template, wherein a window of the dielectric layer is etched to expose the silicon substrate , and wherein the window of the dielectric layer is shaped to limit a size of contact surface exposed over the silicon substrate; and growing a semiconductor material in the window of the dielectric layer to form a buffer layer, wherein the semiconductor material is further grown on the buffer layer to obtain a semiconductor layer, the limited size of the contact surface to reduce threading dislocations of the semiconductor material within the window of the dielectric layer.

2. The method according to claim 1, wherein the size of the contact surface is based on a bottom horizontal size of the window of the dielectric layer, and wherein the bottom horizontal size is not greater than 20 nm.

3. The method according to claim 1, wherein the semiconductor material is a III-V semiconductor material.

4. The method according to claim 1, further comprising: sheltering a partial region of the patterned template using a photoresist so that the silicon layer under the sheltered region is not etched.

5. The method according to claim 4, wherein the method further comprises: producing a waveguide in the silicon layer that is not etched.

6. A method for producing a semiconductor device, comprising: forming a second dielectric layer on a silicon layer of SOI, wherein the SOI comprises a silicon substrate, a first dielectric layer on the silicon substrate, and the silicon layer on the first dielectric layer; etching the second dielectric layer using a patterned template as a mask, and wherein a window of the second dielectric layer is etched to expose the silicon layer, and wherein the window of the second dielectric layer is shaped to limit a size of contact surface exposed over the silicon layer; and growing a semiconductor material in the window of the second dielectric layer to form a buffer layer, wherein the semiconductor material is further grown on the buffer layer to obtain a semiconductor layer, the limited size of the contact surface to reduce threading dislocations of the semiconductor material within the window of the second dielectric layer.

7. The method according to claim 6, wherein the size of the contact surface is based on a bottom horizontal size of the window of the second dielectric layer, and wherein the bottom horizontal size is not greater than 20 nm.

8. The method according to claim 6, wherein the semiconductor material is a III-V semiconductor material.

9. The method according to claim 6, wherein further comprising: producing a ridge waveguide in the silicon layer.

10. The method according to claim 9, wherein further comprising: sheltering a partial region of the patterned template using a photoresist, wherein a region that is not sheltered by the photoresist corresponds to a position of the ridge waveguide.

11. A semiconductor device, comprising: a first silicon layer; a first dielectric layer, which is formed on the first silicon layer, wherein a window of the first dielectric layer is etched to expose the first silicon layer, and wherein the window of the first dielectric layer is shaped to limit a size of contact surface exposed over the first silicon layer; and a semiconductor material layer, wherein the semiconductor material layer is grown on the first dielectric layer, wherein a part of the semiconductor material layer is grown into the window of the first dielectric layer and in contact with the first silicon layer over the contact surface, wherein the limited size of the contact surface is configured to reduce threading dislocations of the semiconductor material layer within the window of the first dielectric layer.

12. The semiconductor device according to claim 11, wherein the size of the contact surface is based on a bottom horizontal size of the window of the first dielectric layer, and wherein the bottom horizontal size is not greater than 20 nm.

13. The semiconductor device according to claim 11, wherein the semiconductor material is a III-V semiconductor material.

14. The semiconductor device according to claim 11, wherein the window of the first dielectric layer is in a shape of an inverted taper or in a shape of a cylinder.

15. The semiconductor device according to claim 11, wherein the semiconductor device further comprises: a second silicon layer on the first dielectric layer, wherein the second silicon layer comprises a waveguide, and wherein the second silicon layer is directly or indirectly connected to the semiconductor material layer to couple light from the semiconductor material layer into the waveguide.

16. The semiconductor device according to claim 11, wherein the first silicon layer comprises a waveguide to couple light output from the semiconductor material layer, and wherein the semiconductor device further comprises: a second dielectric layer under the first silicon layer; and a third silicon layer under the second dielectric layer, wherein the third silicon layer is a silicon substrate.

17. The semiconductor device according to claim 11, wherein the semiconductor device is a laser, wherein the semiconductor material layer comprises a buffer layer, an active region, an interlayer, an N-type doped transition layer, and a P-type doped transition layer, and wherein the semiconductor device further comprises an N electrode and a P electrode, wherein the N electrode is connected to the N-type doped transition layer, and the P electrode is connected to the P-type doped transition layer.

18. The semiconductor device according to claim 11, wherein the semiconductor device is an optical amplifier, wherein the semiconductor material layer comprises a buffer layer, an active region, an interlayer, an N-type doped transition layer, and a P-type doped transition layer, and wherein the semiconductor device further comprises an N electrode, a P electrode, and an antireflective film on an end face of the semiconductor material layer, wherein the N electrode is connected to the N-type doped transition layer, the P electrode is connected to the P-type doped transition layer.

19. The semiconductor device according to claim 11, wherein the semiconductor device is a photodetector, wherein the semiconductor material layer comprises an N region, a P region, and an intrinsic region, and wherein the semiconductor device further comprises an N electrode and a P electrode, wherein the N electrode is connected to the N region, and the P electrode is connected to the P region.

20. The semiconductor device according to claim 11, wherein the semiconductor device is a transistor, wherein the semiconductor material layer is a channel material of the transistor, and wherein the semiconductor device further comprises a source, a drain, a gate, and a gate dielectric layer, wherein the source, the drain, and the gate dielectric layer are connected to the semiconductor material layer, and the gate is connected to the gate dielectric layer.
Description



CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of International Application No. PCT/CN2013/090099, filed on Dec. 20, 2013, which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

[0002] The present disclosure relates to the field of information technologies, and in particular, to a semiconductor device and a method for producing a semiconductor device.

BACKGROUND

[0003] To improve performance of a microprocessor, an integrated circuit always keeps high-speed development of miniaturization and diversification. However, a reduction in device size and an increase in device density also cause some inevitable problems, for example, a signal delay and interconnect crosstalk. Due to high power consumption and a waste of energy caused by usage of an electrical interconnection medium, a requirement of high performance and low costs for a device in the semiconductor industry gradually cannot be met. It is found that optical interconnection can effectively resolve these problems and bring about many new functions to a conventional integrated circuit. Therefore, silicon photonics becomes an important research subject of a future optoelectronic integrated circuit.

[0004] Silicon is a foundation stone of a microelectronic platform, is also indispensable for optoelectronic integration, and has advantages of high integration and low costs. Oxides of the silicon are excellent insulating materials, have a relatively high refractive-index difference, and may be used to guide light. However, the silicon is an indirect bandgap semiconductor and has very low efficiency in light absorption and emission; in addition, carrier mobility of the silicon is not high, leading to limitations to an application involving a high speed. On the contrary, a III-V compound semiconductor has a direct bandgap structure and high electron mobility, and a low dimensional system of the III-V compound semiconductor, for example, a multi-quantum well or a quantum dot, brings about much excellent performance to an optical gain, and brings about diverse changes to a device performance parameter by means of adjustment on material composition and optimization on a low dimensional structure. The III-V compound semiconductor may be used to produce a optoelectronic device such as a laser or a solar cell, and an electronic device, such as a high electron mobility transistor.

[0005] A monolithic integration technology for producing a III-V semiconductor device is epitaxially growing a III-V material on a silicon substrate, to produce a device. However, because there are significant lattice mismatch and thermal mismatch between the silicon and a III-V material such as gallium arsenide or indium phosphide, directly growing the III-V material on the silicon leads to high-density threading dislocations, causing a degradation of device performance and a reduction in reliability.

SUMMARY

[0006] Embodiments of the present disclosure provide a semiconductor device and a method for producing a semiconductor device, which can provide a III-V semiconductor device without a threading dislocation.

[0007] According to a first aspect, a semiconductor device is provided, including:

[0008] a first silicon layer;

[0009] a first dielectric layer, where the first dielectric layer is located on the first silicon layer, the first dielectric layer has a window, and a bottom horizontal size of the window of the first dielectric layer is not greater than 20 nm; and

[0010] a III-V semiconductor layer, where the III-V semiconductor layer is distributed on the first dielectric layer, goes deeply into the window of the first dielectric layer, and is connected to the first silicon layer in the window of the first dielectric layer.

[0011] With reference to the first aspect, in a first possible implementation manner, the window of the first dielectric layer is in a shape of an inverted taper or of a cylinder.

[0012] With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner, the first silicon layer is a silicon substrate; and

[0013] the semiconductor device further includes:

[0014] a second silicon layer, where the second silicon layer includes a waveguide, the second silicon layer is located on the first dielectric layer, a part, between the second silicon layer and the first silicon layer, of the first dielectric layer has no window, and the second silicon layer is directly or indirectly connected to the III-V semiconductor layer.

[0015] With reference to the first aspect or the first possible implementation manner of the first aspect, in a third possible implementation manner, the first silicon layer includes a waveguide, where the window of the first dielectric layer is located on the waveguide; and

[0016] the semiconductor device further includes:

[0017] a second dielectric layer and a third silicon layer, where the third silicon layer is a silicon substrate, and the second dielectric layer is located under the first silicon layer and on the third silicon layer.

[0018] With reference to the first aspect or any possible implementation manner of the first to third possible implementation manners of the first aspect, in a fourth possible implementation manner, the semiconductor device is a laser;

[0019] the III-V semiconductor layer includes a buffer layer, an active region, an interlayer, an N-type doped transition layer, and a P-type doped transition layer; and

[0020] the semiconductor device further includes an N electrode and a P electrode, where the N electrode is connected to the N-type doped transition layer, and the P electrode is connected to the P-type doped transition layer.

[0021] With reference to the first aspect or any possible implementation manner of the first to third possible implementation manners of the first aspect, in a fifth possible implementation manner, the semiconductor device is an optical amplifier;

[0022] the III-V semiconductor layer includes a buffer layer, an active region, an interlayer, an N-type doped transition layer, and a P-type doped transition layer; and

[0023] the semiconductor device further includes an N electrode, a P electrode, and an antireflective film, where the N electrode is connected to the N-type doped transition layer, the P electrode is connected to the P-type doped transition layer, and the antireflective film is located on an end face of the III-V semiconductor layer.

[0024] With reference to the first aspect or any possible implementation manner of the first to third possible implementation manners of the first aspect, in a sixth possible implementation manner, the semiconductor device is a photodetector;

[0025] the III-V semiconductor layer includes an N region, a P region, and an intrinsic region; and

[0026] the semiconductor device further includes an N electrode and a P electrode, where the N electrode is connected to the N region, and the P electrode is connected to the P region.

[0027] With reference to the first aspect or the first possible implementation manner of the first aspect, in a seventh possible implementation manner, the semiconductor device is a transistor;

[0028] the III-V semiconductor layer is a channel material of the transistor; and

[0029] the semiconductor device further includes a source, a drain, a gate, and a gate dielectric layer, where the source, the drain, and the gate dielectric layer are connected to the III-V semiconductor layer, and the gate is connected to the gate dielectric layer.

[0030] According to a second aspect, a method for producing a semiconductor device is provided, including:

[0031] etching a silicon layer of SOI using a patterned template as a mask, where the SOI includes a silicon substrate, a dielectric layer on the silicon substrate, and the silicon layer on the dielectric layer; and when the dielectric layer is exposed, stopping the etching and removing the patterned template so that the silicon layer has a window;

[0032] etching the dielectric layer using the silicon layer having the window as a template, and when the silicon substrate is exposed, stopping the etching and removing the silicon layer having the window so that the dielectric layer has a window, where a bottom horizontal size of the window of the dielectric layer is not greater than 20 nm; and

[0033] growing a semiconductor material in the window of the dielectric layer to form a buffer layer, and continuing to grow the semiconductor material on the buffer layer to obtain a semiconductor layer.

[0034] With reference to the second aspect, in a first possible implementation manner, the patterned template is a porous alumina membrane or a photoresist after exposure to extreme ultraviolet and development.

[0035] With reference to the second aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner, the semiconductor material is a III-V semiconductor material.

[0036] With reference to the second aspect or the first or second possible implementation manner of the second aspect, in a third possible implementation manner, the semiconductor material includes a preset quantity of doped materials.

[0037] With reference to the second aspect or any possible implementation manner of the first to third possible implementation manners of the second aspect, in a fourth possible implementation manner, before the etching a silicon layer of SOI using a patterned template as a mask, the method further includes:

[0038] sheltering a partial region of the patterned template using a photoresist so that the silicon layer under the sheltered region is not etched.

[0039] With reference to the fourth possible implementation manner of the second aspect, in a fifth possible implementation manner, the method further includes:

[0040] producing a waveguide in the silicon layer that is not etched.

[0041] According to a third aspect, a method for producing a semiconductor device is provided, including:

[0042] producing a waveguide in a silicon layer of SOI, where the SOI includes a silicon substrate, a first dielectric layer on the silicon substrate, and the silicon layer on the first dielectric layer;

[0043] forming a second dielectric layer on the silicon layer;

[0044] etching the second dielectric layer using a patterned template as a mask, and when the silicon layer is exposed, stopping the etching and removing the patterned template so that the second dielectric layer has a window, where a bottom horizontal size of the window of the second dielectric layer is not greater than 20 nm; and

[0045] growing a semiconductor material in the window of the second dielectric layer to form a buffer layer, and continuing to grow the semiconductor material on the buffer layer to obtain a semiconductor layer.

[0046] With reference to the third aspect, in a first possible implementation manner, the patterned template is a porous alumina membrane or a photoresist after exposure to extreme ultraviolet and development.

[0047] With reference to the third aspect or the first possible implementation manner of the third aspect, in a second possible implementation manner, the semiconductor material is a III-V semiconductor material.

[0048] With reference to the third aspect or the first or second possible implementation manner of the third aspect, in a third possible implementation manner, the semiconductor material includes a preset quantity of doped materials.

[0049] With reference to the third aspect or any possible implementation manner of the first to third possible implementation manners of the third aspect, in a fourth possible implementation manner, the producing a waveguide in a silicon layer of silicon on insulator (SOI) includes:

[0050] producing a ridge waveguide in the silicon layer.

[0051] With reference to the fourth possible implementation manner of the third aspect, in a fifth possible implementation manner, before the etching the second dielectric layer using a patterned template as a mask, the method further includes:

[0052] sheltering a partial region of the patterned template using a photoresist, where a region that is not sheltered by the photoresist corresponds to a position of the ridge waveguide.

[0053] Based on the foregoing technical solutions, for the semiconductor device in the embodiments of the present disclosure, a III-V semiconductor material is used, and the III-V semiconductor material of the semiconductor device in the embodiments of the present disclosure has no threading dislocations; therefore, the semiconductor device has relatively high performance.

BRIEF DESCRIPTION OF DRAWINGS

[0054] The following briefly describes the accompanying drawings required for describing the embodiments of the present disclosure.

[0055] FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;

[0056] FIG. 2 is a schematic structural diagram of a semiconductor device according to another embodiment of the present disclosure;

[0057] FIG. 3 is a schematic structural diagram of a laser according to an embodiment of the present disclosure;

[0058] FIG. 4 is a schematic structural diagram of an optical amplifier according to an embodiment of the present disclosure;

[0059] FIG. 5 is a schematic structural diagram of a detector according to an embodiment of the present disclosure;

[0060] FIG. 6 is a schematic structural diagram of a detector according to another embodiment of the present disclosure;

[0061] FIG. 7 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure;

[0062] FIG. 8 is a schematic structural diagram of monolithic integration of a transistor according to an embodiment of the present disclosure;

[0063] FIG. 9 is a schematic structural diagram of a semiconductor device according to another embodiment of the present disclosure;

[0064] FIG. 10 is a schematic structural diagram of a laser according to another embodiment of the present disclosure;

[0065] FIG. 11 is a schematic structural diagram of an optical amplifier according to another embodiment of the present disclosure;

[0066] FIG. 12 is a schematic structural diagram of a detector according to another embodiment of the present disclosure;

[0067] FIG. 13 is a schematic structural diagram of a detector according to another embodiment of the present disclosure;

[0068] FIG. 14 is a schematic flowchart of a method for producing a semiconductor device according to an embodiment of the present disclosure;

[0069] FIG. 15 is schematic diagrams of a semiconductor device at different stages in a method for producing a semiconductor device according to an embodiment of the present disclosure;

[0070] FIG. 16 is a schematic flowchart of a method for producing a semiconductor device according to another embodiment of the present disclosure; and

[0071] FIG. 17 is schematic diagrams of a semiconductor device at different stages in a method for producing a semiconductor device according to another embodiment of the present disclosure.

DESCRIPTION OF EMBODIMENTS

[0072] The following describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure.

[0073] It should be understood that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different content, and no other limitation is set to the embodiments of the present disclosure.

[0074] FIG. 1 is a schematic structural diagram of a semiconductor device 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the semiconductor device 100 includes a first silicon layer 110, a first dielectric layer 120, and a III-V semiconductor layer 130.

[0075] The first silicon layer 110 is a silicon substrate.

[0076] The first dielectric layer 120 is located on the first silicon layer 110. A material of the first dielectric layer 120 may be silicon oxide, or silicon nitride, or a mixture thereof.

[0077] The first dielectric layer 120 has a window 121, and a bottom horizontal size of the window 121 is not greater than 20 nm. A quantity of windows 121 is not limited, and may change according to a size of the semiconductor device 100.

[0078] The III-V semiconductor layer 130 is distributed on the first dielectric layer 120 and goes deeply into the window 121 of the first dielectric layer 120. The III-V semiconductor layer 130 is connected to the first silicon layer 110 in the window 121 of the first dielectric layer 120.

[0079] The III-V semiconductor layer 130 may be obtained by first growing a III-V semiconductor material in the window 121 and then continuing to grow the III-V semiconductor material on the first dielectric layer 120. The III-V semiconductor material may include one or more of the following:

[0080] aluminium phosphide (AlP), gallium phosphide (GaP), indium phosphide (InP), aluminium arsenide (AlAs), gallium arsenide (GaAs), indium arsenide (InAs), aluminium antimonide (AlSb), gallium antimonide (GaSb), indium antimonide (InSb), aluminium nitride (AlN), gallium nitride (GaN), indium nitride (InN), and ternary and quaternary compounds thereof.

[0081] In this embodiment of the present disclosure, the bottom horizontal size of the window 121 of the first dielectric layer 120 is not greater than 20 nm, that is, a size of a contact surface between the III-V semiconductor layer 130 and the first silicon layer 110 is not greater than 20 nm in any direction; in this way, the III-V semiconductor material in the window 121 (this means, the III-V semiconductor material on the contact surface) has no threading dislocations. That is, the semiconductor device in this embodiment of the present disclosure is a III-V semiconductor device without a threading dislocation. Because the III-V semiconductor material has a direct bandgap structure and relatively high electron mobility, which can improve performance of the semiconductor device, the semiconductor device in this embodiment of the present disclosure has relatively high crystalline quality and device performance.

[0082] Therefore, for the semiconductor device in this embodiment of the present disclosure, a III-V semiconductor material is used; the III-V semiconductor material has no threading dislocations, and therefore has relatively high performance.

[0083] In this embodiment of the present disclosure, optionally, the window 121 of the first dielectric layer 120 may be in a shape of an inverted taper or of a cylinder. In other words, in this embodiment of the present disclosure, only the bottom horizontal size of the window 121 is limited to be not greater than 20 nm, but a shape of the window 121 is not limited, that is, the window 121 may also be in another shape. Furthermore, when the window 121 is in a shape of an inverted taper or of a cylinder, a bottom diameter of the window 121 is not greater than 20 nm; when the window 121 is in another shape, the bottom horizontal size of the window 121 is not greater than 20 nm.

[0084] In this embodiment of the present disclosure, optionally, as shown in FIG. 2, the semiconductor device 100 further includes:

[0085] a second silicon layer 140.

[0086] The second silicon layer 140 is located on the first dielectric layer 120, and a part, between the second silicon layer 140 and the first silicon layer 110, of the first dielectric layer 120 has no window. That is, the second silicon layer 140 is located on the part that has no window and that is of the first dielectric layer 120. The second silicon layer 140 is directly or indirectly connected to the III-V semiconductor layer 130. The second silicon layer 140 includes a waveguide, and light output from the III-V semiconductor layer 130 may be coupled into the waveguide.

[0087] Optionally, the semiconductor device 100 may further include a filling layer 150. The filling layer 150 is used to fill a gap between the III-V semiconductor layer 130 and the second silicon layer 140. For example, a material such as amorphous silicon may be used to fill the gap.

[0088] Optionally, the semiconductor device 100 in this embodiment of the present disclosure may be specifically a laser, an optical amplifier, a photodetector, a transistor, a solar cell, or the like.

[0089] FIG. 3 is a schematic structural diagram of a laser according to an embodiment of the present disclosure.

[0090] As shown in FIG. 3, in this embodiment, the semiconductor device 100 is a laser.

[0091] In this embodiment, the III-V semiconductor layer 130 constitutes a main structure of the laser, including a buffer layer 131, an active region 134, an interlayer 133, an N-type doped transition layer 132, and a P-type doped transition layer 135.

[0092] The III-V semiconductor material in the window 121 forms the buffer layer 131, and the semiconductor material in the buffer layer 131 has no threading dislocations.

[0093] Light of the laser is generated and amplified in the active region 134. The active region 134 may include a multi-quantum well or a quantum dot, to improve an optical gain.

[0094] In this embodiment, the semiconductor device 100 further includes an N electrode 160 and a P electrode 170, where the N electrode 160 is connected to the N-type doped transition layer 132, and the P electrode 170 is connected to the P-type doped transition layer 135. Optionally, the semiconductor device 100 may further include a grating structure.

[0095] Light output from the main structure of the laser is coupled into the waveguide in the second silicon layer 140.

[0096] For the laser in this embodiment, a III-V semiconductor material is used to form a main structure of the laser, and the III-V semiconductor material has no threading dislocations; therefore, the laser has relatively high performance.

[0097] FIG. 4 is a schematic structural diagram of an optical amplifier according to an embodiment of the present disclosure.

[0098] As shown in FIG. 4, in this embodiment, the semiconductor device 100 is an optical amplifier, which is also referred to as a semiconductor optical amplifier (SOA).

[0099] Similar to the forgoing embodiment of the laser, the III-V semiconductor layer 130 constitutes a main structure of the optical amplifier, including a buffer layer 131, an active region 134, an interlayer 133, an N-type doped transition layer 132, and a P-type doped transition layer 135.

[0100] The III-V semiconductor material in the window 121 forms the buffer layer 131, and the semiconductor material in the buffer layer 131 has no threading dislocations.

[0101] Light input into the optical amplifier from outside is amplified in the active region 134. The active region 134 may include a bulk material, a multi-quantum well, a quantum dot, a quantum wire, or the like.

[0102] In this embodiment, the semiconductor device 100 further includes an N electrode 160, a P electrode 170, and an antireflective film 180. The N electrode 160 is connected to the N-type doped transition layer 132, and the P electrode 170 is connected to the P-type doped transition layer 135. The antireflective film 180 is located on an end face of the III-V semiconductor layer 130, and the antireflective film is also referred to as an anti-reflection coating.

[0103] Light output from the main structure of the optical amplifier is coupled into the waveguide in the second silicon layer 140.

[0104] For the optical amplifier in this embodiment, a III-V semiconductor material is used to form a main structure of the optical amplifier, and the III-V semiconductor material has no threading dislocations; therefore, the optical amplifier has relatively high performance.

[0105] FIG. 5 and FIG. 6 are schematic structural diagrams of a photodetector according to an embodiment of the present disclosure.

[0106] In this embodiment, the semiconductor device 100 is a photodetector.

[0107] As shown in FIG. 5 and FIG. 6, the III-V semiconductor layer 130 includes an N region 136, a P region 137, and an intrinsic region 138.

[0108] The N region 136 and the P region 137 are doped regions. The N region 136 and the P region 137 may be vertically distributed (as shown in FIG. 5), and may also be distributed on a device surface (as shown in FIG. 6).

[0109] The semiconductor device 100 further includes an N electrode 160 and a P electrode 170. The N electrode 160 is connected to the N region 136, and the P electrode 170 is connected to the P region 137.

[0110] Light is coupled into the detector from the waveguide in the second silicon layer 140, so as to be detected.

[0111] For the photodetector in this embodiment, a III-V semiconductor material is used, and the III-V semiconductor material has no threading dislocations; therefore, the photodetector has relatively high performance.

[0112] FIG. 7 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure.

[0113] As shown in FIG. 7, in this embodiment, the semiconductor device 100 is a transistor.

[0114] The III-V semiconductor layer 130 is a channel material of the transistor, that is, the transistor in this embodiment of the present disclosure is a III-V semiconductor transistor. The channel material may include a multi-quantum well or a quantum dot.

[0115] The semiconductor device 100 further includes a source 181, a drain 182, a gate 183, and a gate dielectric layer 184. The source 181, the drain 182, and the gate dielectric layer 184 are connected to the III-V semiconductor layer 130, and the gate 183 is connected to the gate dielectric layer 184.

[0116] The III-V semiconductor transistor in this embodiment of the present disclosure may be monolithically integrated with a Si transistor, as shown in FIG. 8.

[0117] Multiple transistors may be obtained by selecting different III-V semiconductor materials as channel materials. For example, a heterojunction constituted by two different bandgap materials is used as a channel material, and a high electron mobility transistor (HEMT) may be obtained. In addition, a metal-semiconductor field effect transistor (MESFET), a fin field effect transistor (FinFET), a modulation doped field effect transistor (MODFET), and the like may be further obtained.

[0118] For the transistor in this embodiment, a III-V semiconductor material is used, and the III-V semiconductor material has no threading dislocations; therefore, the transistor has relatively high performance.

[0119] FIG. 9 is a schematic structural diagram of a semiconductor device 200 according to another embodiment of the present disclosure. As shown in FIG. 9, the semiconductor device 200 includes a first silicon layer 210, a first dielectric layer 220, and a III-V semiconductor layer 230.

[0120] The first dielectric layer 220 is located on the first silicon layer 210. A material of the first dielectric layer 220 may be silicon oxide, or silicon nitride, or a mixture thereof.

[0121] The first dielectric layer 220 has a window 221, and a bottom horizontal size of the window 221 is not greater than 20 nm. A quantity of windows 221 is not limited, and may vary with a size of the semiconductor device 200.

[0122] The III-V semiconductor layer 230 is distributed on the first dielectric layer 220 and goes deeply into the window 221 of the first dielectric layer 220. The III-V semiconductor layer 230 is connected to the first silicon layer 210 in the window 221 of the first dielectric layer 220.

[0123] The III-V semiconductor layer 230 may be obtained by first growing a III-V semiconductor material in the window 221, and continuing to grow the III-V semiconductor material on the first dielectric layer 220. The III-V semiconductor material may include one or more of the following:

[0124] aluminium phosphide (AlP), gallium phosphide (GaP), indium phosphide (InP), aluminium arsenide (AlAs), gallium arsenide (GaAs), indium arsenide (InAs), aluminium antimonide (AlSb), gallium antimonide (GaSb), indium antimonide (InSb), aluminium nitride (AlN), gallium nitride (GaN), indium nitride (InN), and ternary and quaternary compounds thereof.

[0125] In this embodiment of the present disclosure, optionally, the first silicon layer 210 includes a waveguide, for example, a ridge waveguide. The window 221 of the first dielectric layer 220 is located on the waveguide.

[0126] Optionally, the semiconductor device 200 further includes:

[0127] a second dielectric layer 240 and a third silicon layer 250.

[0128] The third silicon layer 250 is a silicon substrate.

[0129] The second dielectric layer 240 is located under the first silicon layer 210 and on the third silicon layer 250. A material of the second dielectric layer 240 is similar to that of the first dielectric layer 220, and may be silicon oxide, or silicon nitride, or a mixture thereof.

[0130] In this embodiment of the present disclosure, the bottom horizontal size of the window 221 of the first dielectric layer 220 is not greater than 20 nm, that is, a size of a contact surface between the III-V semiconductor layer 230 and the first silicon layer 210 is not greater than 20 nm in any direction; in this way, the III-V semiconductor material in the window 221 (this means, the III-V semiconductor material on the contact surface) has no threading dislocations. That is, the semiconductor device in this embodiment of the present disclosure is a III-V semiconductor device without a threading dislocation. Because the III-V semiconductor material has a direct bandgap structure and relatively high electron mobility, which can improve performance of the semiconductor device, the semiconductor device in this embodiment of the present disclosure has relatively high crystalline quality and device performance.

[0131] In this embodiment of the present disclosure, optionally, the window 221 of the first dielectric layer 220 may be in a shape of an inverted taper or of a cylinder. In other words, in this embodiment of the present disclosure, only the bottom horizontal size of the window 221 is limited to be not greater than 20 nm, but a shape of the window 221 is not limited, that is, the window 221 may also be in another shape. Furthermore, when the window 221 is in a shape of an inverted taper or of a cylinder, a bottom diameter of the window 221 is not greater than 20 nm; when the window 221 is in another shape, the bottom horizontal size of the window 221 is not greater than 20 nm in any direction.

[0132] Similar to the semiconductor device 100 described above, the semiconductor device 200 in this embodiment of the present disclosure may be specifically a laser, an optical amplifier, a photodetector, a transistor, a solar cell, or the like.

[0133] FIG. 10 is a schematic structural diagram of a laser according to another embodiment of the present disclosure.

[0134] As shown in FIG. 10, in this embodiment, the semiconductor device 200 is a laser.

[0135] In this embodiment, the III-V semiconductor layer 230 constitutes a main structure of the laser, including a buffer layer 231, an active region 234, an interlayer 233, an N-type doped transition layer 232, and a P-type doped transition layer 235.

[0136] The III-V semiconductor material in the window 221 forms the buffer layer 231, and the semiconductor material in the buffer layer 231 has no threading dislocations.

[0137] Light of the laser is generated and amplified in the active region 234. The active region 234 may include a multi-quantum well or a quantum dot, to improve an optical gain.

[0138] In this embodiment, the semiconductor device 200 further includes an N electrode 260 and a P electrode 270, where the N electrode 260 is connected to the N-type doped transition layer 232, and the P electrode 270 is connected to the P-type doped transition layer 235. Optionally, the semiconductor device 200 may further include a grating structure.

[0139] Light output from the main structure of the laser is coupled into the waveguide in the first silicon layer 210.

[0140] For the laser in this embodiment, a III-V semiconductor material is used to form a main structure of the laser, and the III-V semiconductor material has no threading dislocations; therefore, the laser has relatively high performance.

[0141] FIG. 11 is a schematic structural diagram of an optical amplifier according to another embodiment of the present disclosure.

[0142] As shown in FIG. 11, in this embodiment, the semiconductor device 200 is an optical amplifier, which is also referred to as a semiconductor optical amplifier SOA.

[0143] The III-V semiconductor layer 230 constitutes a main structure of the optical amplifier, including a buffer layer 231, an active region 234, an interlayer 233, an N-type doped transition layer 232, and a P-type doped transition layer 235.

[0144] The III-V semiconductor material in the window 221 forms the buffer layer 231, and the semiconductor material in the buffer layer 231 has no threading dislocations.

[0145] Light input into the optical amplifier from outside is amplified in the active region 234. The active region 234 may include a semiconductor material, a multi-quantum well, a quantum dot, a quantum wire, or the like.

[0146] In this embodiment, the semiconductor device 200 further includes an N electrode 260 and a P electrode 270. The N electrode 260 is connected to the N-type doped transition layer 232, and the P electrode 270 is connected to the P-type doped transition layer 235. The semiconductor device 200 further includes an antireflective film, located on an end face of the III-V semiconductor layer.

[0147] Light output from the main structure of the optical amplifier is coupled into the waveguide in the first silicon layer 210.

[0148] For the optical amplifier in this embodiment, a III-V semiconductor material is used to form a main structure of the optical amplifier, and the III-V semiconductor material has no threading dislocations; therefore, the optical amplifier has relatively high performance.

[0149] FIG. 12 and FIG. 13 are schematic structural diagrams of a photodetector according to another embodiment of the present disclosure.

[0150] In this embodiment, the semiconductor device 200 is a photodetector.

[0151] As shown in FIG. 12 and FIG. 13, the III-V semiconductor layer 230 includes an N region 236, a P region 237, and an intrinsic region 238.

[0152] The N region 236 and the P region 237 are doped regions. The N region 236 and the P region 237 may be vertically distributed (as shown in FIG. 12), and may also be distributed on a device surface (as shown in FIG. 13).

[0153] The semiconductor device 200 further includes an N electrode 260 and a P electrode 270. The N electrode 260 is connected to the N region 236, and the P electrode 270 is connected to the P region 237.

[0154] Light is coupled into the detector from the waveguide in the first silicon layer 210, so as to be detected.

[0155] For the photodetector in this embodiment, a III-V semiconductor material is used, and the III-V semiconductor material has no threading dislocations; therefore, the photodetector has relatively high performance.

[0156] The foregoing describes in detail the semiconductor device in the embodiments of the present disclosure, and a method for producing a semiconductor device in an embodiment of the present disclosure is described in detail in the following.

[0157] FIG. 14 is a schematic flowchart of a method 300 for producing a semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 14, the method 300 includes:

[0158] S310: Etch a silicon layer of Silicon On Insulator (SOI) using a patterned template as a mask, where the SOI includes a silicon substrate, a dielectric layer on the silicon substrate, and the silicon layer on the dielectric layer; and when the dielectric layer is exposed, stop the etching and remove the patterned template so that the silicon layer has a window.

[0159] S320: Etch the dielectric layer using the silicon layer having the window as a template, and when the silicon substrate is exposed, stop the etching and remove the silicon layer having the window so that the dielectric layer has a window, where a bottom horizontal size of the window of the dielectric layer is not greater than 20 nm.

[0160] S330: Grow a semiconductor material in the window of the dielectric layer to form a buffer layer, and continue to grow the semiconductor material on the buffer layer to obtain a semiconductor layer.

[0161] FIG. 15 is schematic diagrams of a semiconductor device at different stages in the method 300. As shown in FIG. 15, SOI includes a silicon substrate 410, a dielectric layer 420, and a silicon layer 440. Different thicknesses of the dielectric layer 420 and the silicon layer 440 may be selected according to different requirements and application of the device.

[0162] In S310, a patterned template 490 is used first to etch the silicon layer of the SOI.

[0163] Optionally, the patterned template 490 is a porous alumina membrane or a photoresist after exposure to extreme ultraviolet and development. If a porous alumina membrane is used, the porous alumina membrane is directly stuck on the silicon layer 440 of the SOI (as shown in figure a in FIG. 15). A thin oxide layer may be formed in advance on the silicon layer 440, facilitating subsequent removing of the porous alumina film. If a photoresist after exposure to extreme ultraviolet and development is used, the photoresist is first coated on the silicon layer 440, then a light source for extreme ultraviolet lithography is used to expose the photoresist, and the patterned template 490 is obtained after development.

[0164] Before etching, a partial region of the patterned template 490 may be sheltered using a photoresist (as shown in figure b in FIG. 15) so that the silicon layer under the sheltered region is not etched.

[0165] The silicon layer 440 may be selectively etched by controlling an etching parameter, without etching the dielectric layer 420 under the silicon layer 440. When the dielectric layer 420 is exposed, etching is stopped.

[0166] Because the patterned template 490 exerts a shadow effect on an etched beam current, a window 441 whose aperture is gradually reduced is formed in the silicon layer 440, that is, a top horizontal size of the window 441 is greater than a bottom horizontal size of the window 441 (as shown in figure b in FIG. 15).

[0167] Next, the patterned template 490 is removed, and a patterned silicon layer 440 having the window 441 is obtained. A removing method may be a chemical method.

[0168] In S320, the patterned silicon layer 440 having the window 441 is used as a template to etch the dielectric layer 420. A window 421 is formed in the dielectric layer 420 (as shown in figure c in FIG. 15). Because of the shadow effect, a bottom horizontal size of the window 421 is less than a top horizontal size of the window 421, that is, the bottom horizontal size of the window 421 of the dielectric layer 420 is quite less than a size of a window of the patterned template 490. Then the silicon layer that is not sheltered is removed (as shown in figure d in FIG. 15).

[0169] In S330, a semiconductor material is selectively grown in the window 421 of the dielectric layer 420 so that a buffer layer is formed first; then, the semiconductor material continues to be grown in the buffer layer so that a semiconductor layer 430 is obtained (as shown in figure e in FIG. 15).

[0170] Before growing the semiconductor material, a remaining part of the silicon layer 440 is protected first, for example, a medium protective layer 155 is formed by using silicon oxide, silicon nitride, or the like.

[0171] Preferably, the semiconductor material is a III-V semiconductor material, which, for example, may be one or more of the following:

[0172] aluminium phosphide (AlP), gallium phosphide (GaP), indium phosphide (InP), aluminium arsenide (AlAs), gallium arsenide (GaAs), indium arsenide (InAs), aluminium antimonide (AlSb), gallium antimonide (GaSb), indium antimonide (InSb), aluminium nitride (AlN), gallium nitride (GaN), indium nitride (InN), and ternary and quaternary compounds thereof.

[0173] Optionally, the growth method may include molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD), and variations thereof. For example, the CVD may include metal-organic chemical vapor deposition (MOCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), ultra high vacuum chemical vapor deposition (UHVCVD), reactive plasma chemical vapor deposition (RPCVD), and the like.

[0174] Optionally, the semiconductor material may further include a preset quantity of doped materials, to form a PN or PIN structure. The grown semiconductor material may form an active region, where the active region may include a structure such as a multi-quantum well or a quantum dot.

[0175] Optionally, the method 300 further includes:

[0176] producing a waveguide in the silicon layer that is not etched.

[0177] As shown in figure f in FIG. 15, a waveguide is produced in the remaining part of the silicon layer 440. In addition, the medium protective layer 155 further needs to be removed, and a gap left behind needs to be filled, to form a filling layer 150. For example, a material such as amorphous silicon may be used to fill the gap.

[0178] Because a size of a window in a dielectric layer obtained by using the method for producing a semiconductor device in this embodiment of the present disclosure is quite less than a size of a window of a patterned template, a relatively small window may be formed in the dielectric layer by controlling the size of the window of the patterned template, so as to meet a condition for growing different III-V semiconductor materials without a threading dislocation. For example, a bottom horizontal size of the window formed in the dielectric layer is not greater than 20 nm, or may be less than 10 nm, or may be even less than 2 nm.

[0179] Because a window whose bottom horizontal size is not greater than 20 nm may be formed in a dielectric layer according to the method for producing a semiconductor device in this embodiment of the present disclosure, a III-V semiconductor material in a semiconductor device produced by using the method for producing a semiconductor device in this embodiment of the present disclosure has no threading dislocations. Therefore, a semiconductor device with relatively high performance can be produced according to the method for producing a semiconductor device in this embodiment of the present disclosure.

[0180] According to the method 300 for producing a semiconductor device in this embodiment of the present disclosure, the semiconductor device 100 in the foregoing embodiment of the present disclosure can be produced, and furthermore, with reference to the specific structure of the laser, the optical amplifier, the photodetector, or the transistor provided in the foregoing embodiment, a corresponding semiconductor device can be produced.

[0181] FIG. 16 is a schematic flowchart of another method 400 for producing a semiconductor device according to another embodiment of the present disclosure. As shown in FIG. 16, the method 400 includes:

[0182] S410: Produce a waveguide in a silicon layer of SOI, where the SOI includes a silicon substrate, a first dielectric layer on the silicon substrate, and the silicon layer on the first dielectric layer.

[0183] S420: Form a second dielectric layer on the silicon layer.

[0184] S430: Etch the second dielectric layer using a patterned template as a mask, and when the silicon layer is exposed, stop the etching and remove the patterned template so that the second dielectric layer has a window, where a bottom horizontal size of the window of the second dielectric layer is not greater than 20 nm.

[0185] S440: Grow a semiconductor material in the window of the second dielectric layer to form a buffer layer, and continue to grow the semiconductor material on the buffer layer to obtain a semiconductor layer.

[0186] FIG. 17 is schematic diagrams of a semiconductor device at different stages in the method 400. As shown in FIG. 17, SOI includes a silicon substrate 510, a first dielectric layer 520, and a silicon layer 540.

[0187] In S410, a waveguide is produced in the silicon layer 540 of the SOI, for example, a ridge waveguide is produced, as shown in figure a in FIG. 17.

[0188] In S420, a second dielectric layer 550 is formed on the silicon layer 540 having the waveguide.

[0189] In S430, the second dielectric layer 550 is etched by using a patterned template 590.

[0190] Optionally, the patterned template 590 is a porous alumina membrane or a photoresist after exposure to extreme ultraviolet and development. Before etching, a partial region of the patterned template 590 may be sheltered using a photoresist, where a region that is not sheltered by the photoresist corresponds to a position of the waveguide (as shown in figure b in FIG. 17).

[0191] The second dielectric layer 550 is etched, to expose the silicon layer 540, and form a window 551 on the second dielectric layer 550 (as shown in figure c in FIG. 17).

[0192] Because the patterned template 590 exerts a shadow effect on an etched beam current, a bottom horizontal size of the window 551 formed on the second dielectric layer 550 is less than a top horizontal size of the window 551. Therefore, a relatively small window may be formed in the second dielectric layer 550 by controlling a size of a window of the patterned template 590, for example, a window whose bottom horizontal size is not greater than 20 nm is formed.

[0193] Next, the photoresist and the patterned template 590 are removed.

[0194] In S440, a semiconductor material is selectively grown in the window 551 of the second dielectric layer 550 so that a buffer layer is formed first, and then the semiconductor material continues to be grown in the buffer layer so that a semiconductor layer 530 is obtained (as shown in figure d in FIG. 17).

[0195] Preferably, the semiconductor material is a III-V semiconductor material, which, for example, may be one or more of the following:

[0196] aluminium phosphide (AlP), gallium phosphide (GaP), indium phosphide (InP), aluminium arsenide (AlAs), gallium arsenide (GaAs), indium arsenide (InAs), aluminium antimonide (AlSb), gallium antimonide (GaSb), indium antimonide (InSb), aluminium nitride (AlN), gallium nitride (GaN), indium nitride (InN), and ternary and quaternary compounds thereof.

[0197] Optionally, the semiconductor material may further include a preset quantity of doped materials.

[0198] Because a window whose bottom horizontal size is not greater than 20 nm may be formed in a dielectric layer according to the method for producing a semiconductor device in this embodiment of the present disclosure, a III-V semiconductor material in a semiconductor device produced by using the method for producing a semiconductor device in this embodiment of the present disclosure has no threading dislocations. Therefore, a semiconductor device with relatively high performance can be produced according to the method for producing a semiconductor device in this embodiment of the present disclosure.

[0199] According to the method 400 for producing a semiconductor device in this embodiment of the present disclosure, the semiconductor device 200 in the foregoing embodiment of the present disclosure can be produced, and furthermore, with reference to the specific structure of the laser, the optical amplifier, the photodetector, or the transistor provided in the foregoing embodiment, a corresponding semiconductor device can be produced.

[0200] It should be understood that sequence numbers of the foregoing processes do not mean execution sequences in various embodiments of the present disclosure. The execution sequences of the processes should be determined according to functions and internal logic of the processes, and should not be construed as any limitation on the implementation processes of the embodiments of the present disclosure.

[0201] A person of ordinary skill in the art may be aware that, in combination with the examples described in the embodiments disclosed in this specification, units and algorithm steps may be implemented by electronic hardware, computer software, or a combination thereof. To clearly describe the interchangeability between the hardware and the software, the foregoing has generally described compositions and steps of each example according to functions. Whether the functions are performed by hardware or software depends on particular applications and design constraint conditions of the technical solutions. A person skilled in the art may use different methods to implement the described functions for each particular application, but it should not be considered that the implementation goes beyond the scope of the present disclosure.

[0202] It may be clearly understood by a person skilled in the art that, for the purpose of convenient and brief description, for a detailed working process of the foregoing system, apparatus, and unit, reference may be made to a corresponding process in the foregoing method embodiments, and details are not described herein again.

[0203] In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the described apparatus embodiment is merely exemplary. For example, the unit division is merely logical function division and may be other division in actual implementation. For example, a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces. The indirect couplings or communication connections between the apparatuses or units may be implemented in electronic, mechanical, or other forms.

[0204] The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. A part or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments of the present disclosure.

[0205] In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in a form of hardware, or may be implemented in a form of a software functional unit.

[0206] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, the integrated unit may be stored in a computer-readable storage medium. Based on such an understanding, the technical solutions of the present disclosure essentially, or the part contributing to the prior art, or all or a part of the technical solutions may be implemented in the form of a software product. The software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform all or a part of the steps of the methods described in the embodiments of the present disclosure. The foregoing storage medium includes: any medium that can store program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc.

[0207] The foregoing descriptions are merely specific embodiments of the present disclosure, but are not intended to limit the protection scope of the present disclosure. Any modification or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present disclosure shall fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

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