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United States Patent Application 20170271008
Kind Code A1
SUZUKI; Kunifumi ;   et al. September 21, 2017

SEMICONDUCTOR MEMORY DEVICE

Abstract

According to one embodiment, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode, and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to transition a resistive state of the memory cell. The control circuit performs a first reset operation by applying a first pulse having a voltage of a first polarity to the memory cell, and applying a second pulse having a voltage of a second polarity that is an inverse of the first polarity to the memory cell after applying the first pulse.


Inventors: SUZUKI; Kunifumi; (Yokkaichi, JP) ; YAMAMOTO; Kazuhiko; (Yokkaichi, JP)
Applicant:
Name City State Country Type

KABUSHIKI KAISHA TOSHIBA

Tokyo

JP
Assignee: KABUSHIKI KAISHA TOSHIBA
Tokyo
JP

Family ID: 1000002196081
Appl. No.: 15/269523
Filed: September 19, 2016


Related U.S. Patent Documents

Application NumberFiling DatePatent Number
62309684Mar 17, 2016

Current U.S. Class: 1/1
Current CPC Class: G11C 13/0064 20130101; G11C 13/0069 20130101
International Class: G11C 13/00 20060101 G11C013/00

Claims



1. A semiconductor memory device, comprising: a first electrode; a second electrode; a memory cell provided between the first electrode and the second electrode, the memory cell including a metal containing film and a resistance change film; and a control circuit that applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell, wherein the control circuit performs a first reset operation, a verify operation and a second reset operation, the first reset operation is performed by applying a first pulse having a voltage of a first polarity to the memory cell, and applying a second pulse having a voltage of a second polarity that is an inverse of the first polarity to the memory cell after applying the first pulse, the verify operation confirms whether the memory cell is in a desired state, performed by applying the memory cell with a verify pulse having the first polarity, the second reset operation is performed by applying a sixth pulse having a larger voltage than a voltage of the second pulse and a second polarity, and the control circuit performs the verify operation every time the first reset operation terminates and performs the second reset operation when the memory cell is out of a desired state after performing the verify operation.

2. The semiconductor memory device according to claim 1, wherein: the control circuit performs a set operation by applying a third pulse having a voltage of the first polarity to the memory cell when transitioning the memory cell to a low resistance state; and the voltage of the first pulse has a lower value than the voltage of the third pulse.

3. The semiconductor memory device according to claim 2, wherein the voltage of the first pulse has a magnitude of equal to or more than 30% and equal to or less than 80% of the voltage of the third pulse.

4-5. (canceled)

6. The semiconductor memory device according to claim 1, wherein: the control circuit applies a further pulse having a voltage of the first polarity to the memory cell when transitioning the memory cell to the low resistance state; and the voltage of the first pulse has a magnitude of equal to or more than 80% of the voltage of the further pulse.

7. The semiconductor memory device according to claim 1, wherein a product of an amplitude and a pulse width of the first pulse is smaller than a product of an amplitude and a pulse width of the second pulse.

8. The semiconductor memory device according to claim 1, wherein the control circuit starts to apply the second pulse within 100 nsec since termination of applying the first pulse.

9. The semiconductor memory device according to claim 1, wherein: the resistance change film is provided between the first electrode and the second electrode; and the metal containing film is provided between the resistance change film and the second electrode.

10. The semiconductor memory device according to claim 1, wherein the control circuit, when transitioning the memory cell to a high resistance state, applies a positive first voltage to the second electrode, and applies a second voltage lower than the first voltage to the second electrode after applying the first voltage.

11. The semiconductor memory device according to claim 10, wherein the control circuit applies a negative third voltage to the first electrode before starting to apply the first voltage, increases the voltage of the first electrode to a positive fourth voltage from the third voltage before starting to apply the second voltage after termination of applying the first voltage, and terminates applying the fourth voltage after termination of applying the second voltage.

12. A semiconductor memory device, comprising: a first wiring; a second wiring intersecting with the first wiring; a memory cell provided between the first wiring and the second wiring, the memory cell including a metal containing film and a resistance change film; and a control circuit that applies any voltage to the first wiring and the second wiring, wherein the control circuit, when transitioning the memory cell to a high resistance state, between the first wiring and the second wiring, applies a first pulse having a voltage of a first polarity and applies a second pulse having a voltage of a second polarity that is an inverse of the first polarity after applying the first pulse, the first pulse is applied by: applying a negative third voltage to the second wiring; and applying a positive first voltage to the first wiring while the third voltage is applied, and the second pulse is applied by: increasing the voltage of the second wiring to a positive fourth voltage from the third voltage after termination of applying the first voltage; applying a second voltage lower than the first voltage to the first wiring after increasing the voltage of the second wiring to the fourth voltage; and terminating applying the fourth voltage after termination of applying the second voltage.

13. The semiconductor memory device according to claim 12, wherein: the control circuit applies a third pulse having a voltage of the first polarity between the first wiring and the second wiring when transitioning the memory cell to a low resistance state; and the voltage of the first pulse has a magnitude of equal to or more than 30% of the voltage of the third pulse.

14. The semiconductor memory device according to claim 12, wherein: the control circuit applies a further pulse having the voltage of the first polarity between the first wiring and the second wiring when transitioning the memory cell to the low resistance state; and the voltage of the first pulse has a magnitude of equal to or more than 80% of the voltage of the further pulse.

15. The semiconductor memory device according to claim 12, wherein a product of an amplitude and a pulse width of the first pulse is smaller than a product of an amplitude and a pulse width of the second pulse.

16. The semiconductor memory device according to claim 12, wherein the control circuit starts to apply the second pulse within 100 nsec since termination of applying the first pulse.

17. The semiconductor memory device according to claim 12, wherein: the resistance change film is provided between the first wiring and the second wiring; and the metal containing film is provided between the resistance change film and the first wiring.

18-20. (canceled)
Description



CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of U.S. Provisional Patent Application No. 62/309,684, filed on Mar. 17, 2016, the entire contents of which are incorporated herein by reference.

FIELD

[0002] Embodiments described herein relate generally to a semiconductor memory device.

BACKGROUND

Description of the Related Art

[0003] As a semiconductor memory device that stores large capacity data for uses, attention has been focused on such as a resistive random access memory (ReRAM: Resistive RAM) that is easily formed three-dimensionally. As such resistive random access memory, CBRAM (Conduction Bridge RAM), for example, is used.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a block diagram illustrating a semiconductor memory device according to a first embodiment.

[0005] FIG. 2 is a circuit diagram illustrating a configuration of a memory cell array of the semiconductor memory device.

[0006] FIG. 3 is a perspective view illustrating the configuration of the memory cell array.

[0007] FIG. 4 is a cross-sectional view illustrating a configuration of a memory cell of the semiconductor memory device.

[0008] FIG. 5 is a schematic diagram for describing a set operation of the semiconductor memory device.

[0009] FIG. 6 is a schematic diagram for describing a reset operation of the semiconductor memory device.

[0010] FIG. 7 is a graph illustrating current-voltage characteristics of the memory cell of the semiconductor memory device.

[0011] FIG. 8 is a circuit diagram for describing an operation of the semiconductor memory device.

[0012] FIG. 9 is a timing diagram for describing the set operation of the semiconductor memory device.

[0013] FIG. 10 is a timing diagram for describing the reset operation of the semiconductor memory device.

[0014] FIG. 11 is a timing diagram for describing a reset operation of a semiconductor memory device according to a comparative example.

[0015] FIG. 12 is a timing diagram for describing a reset operation according to a second embodiment.

[0016] FIG. 13 is a flowchart for describing a set operation according to a third embodiment.

[0017] FIG. 14 is a timing diagram for describing the set operation.

[0018] FIG. 15 is a flowchart for describing a reset operation according to a fourth embodiment.

[0019] FIG. 16 is a timing diagram for describing the reset operation.

DETAILED DESCRIPTION

[0020] A semiconductor memory device according to one embodiment includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode, and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell. The control circuit performs a first reset operation by applying a first pulse to the memory cell and applying a second pulse to the memory cell after applying the first pulse. The first pulse has a voltage of a first polarity. The second pulse has a voltage of a second polarity that is an inverse of the first polarity.

[0021] Next, a description will be given of the semiconductor memory device according to the embodiments in detail with reference to the drawings. Here, these embodiments are only examples, and are not described for the purpose of limiting the present invention.

[0022] For example, the drawings used in the following embodiments are schematically illustrated. The thickness, the width, and the ratio of the layer, and the magnitude, the application time, and the ratio of the voltage, or similar parameter may be different from actual parameters.

[0023] In the following description, as a structure of a memory cell array, a configuration including one layer of memory mat is indicated as an example. However, the present invention may be applicable to a configuration including two or more laminated layers of memory mats. The present invention may also be applicable to a configuration with a bit line extending to a direction intersecting with a surface of a substrate, which is so-called VBL (Vertical Bit Line) type.

First Embodiment

[0024] [Overall Configuration]

[0025] FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment. Here, the semiconductor memory device means, for example, a chip C that stores user data, an electronic device that includes the chip C (such as a smart phone, a mobile phone, a tablet terminal, a music player, and a wearable device), or the like. The user data is data to express, for example, contents used by a user (such as a character string, an audio, an image and a moving image), which are expressed by combinations of "0" and "1."

[0026] The chip C includes a memory cell array 11, a row decoder 12, a column decoder 13, an upper block decoder 14, a power supply 15, and a control circuit 16.

[0027] The memory cell array 11 includes a plurality of memory cells MC that store data of 1 bit or a plurality of bits. The memory cell array 11 is configured such that an access (data erasure/writing/reading) to a desired memory cell MC can be performed by applying a predetermined voltage to desired bit line BL and word line WL corresponding to address data.

[0028] The row decoder 12 selects one word line WL corresponding to a row address for access to apply the predetermined voltage.

[0029] The column decoder 13 selects one or the plurality of bit lines BL corresponding to a column address for access to apply the predetermined voltage. The column decoder 13 includes a sense amplifier circuit for detecting the current or the voltage of the bit line BL to determine the user data recorded on the memory cell MC.

[0030] The upper block decoder 14 generates the row address and the column address corresponding to the address data to supply to the row decoder 12 and the column decoder 13.

[0031] The power supply 15 generates combinations of the predetermined voltages corresponding to each operation of data erasure/writing/reading to supply to the row decoder 12 and the column decoder 13.

[0032] The control circuit 16 accepts external control signals from an external host (not illustrated) to control such as the upper block decoder 14 and the power supply 15.

[0033] FIG. 2 is an equivalent circuit diagram illustrating a configuration of a part of the memory cell array 11.

[0034] The memory cell array 11 includes the plurality of bit lines BL (second wiring), the plurality of word lines WL (first wiring), and the plurality of memory cells MC connected to these bit lines BL and word lines WL. These memory cells MC are connected to the column decoder 13 via the bit line BL (FIG. 1) and to the row decoder 12 via the word line WL (FIG. 1). The plurality of memory cells MC connected to the common word lines WL store user data for one page, for example. The plurality of memory cells MC each store data for one bit, for example.

[0035] The memory cell MC serves as a variable resistive element to vary its resistance value corresponding to the stored data. For example, the memory cell MC that records "0" is in a high resistance state, and the memory cell MC that records "1" is in a low resistance state.

[0036] FIG. 3 is a schematic perspective view illustrating the configuration of a part of the memory cell array 11. FIG. 3 is a drawing for describing a three-dimensional structure of wirings, the memory cells MC, and similar part. Then, the interlayer insulating films provided such as between the wirings are not illustrated. FIG. 3 is a drawing for an explanation. Then, the specific configuration may be changed as necessary.

[0037] As illustrated in FIG. 3, the memory cell array 11 is, for example, what is called a cross-point type memory cell array. That is, in the memory cell array 11, a plurality of bit lines BL arranged in an X direction, provided in parallel and extending in a Y direction is provided. Above the plurality of bit lines BL, a plurality of word lines WL arranged in the Y direction, provided in parallel and extending in the X direction is provided. Furthermore, at the intersecting portions between the plurality of bit lines BL and the plurality of word lines WL, the respective memory cells MC are provided.

[0038] [Memory Cell MC]

[0039] FIG. 4 is a cross-sectional view illustrating a configuration of a part of the memory cell MC. In FIG. 4, interlayer insulating films provided between the likes of the wirings or the like are not illustrated.

[0040] The memory cell MC is provided between a lower electrode 101 (cathode, the first electrode) connected to the bit line BL and an upper electrode 104 (anode, the second electrode) connected to the word line WL. The memory cell MC includes a resistance change film 102 provided between the lower electrode 101 and the upper electrode 104, and a metal film 103 provided between this resistance change film 102 and the upper electrode 104. The memory cell MC may be in two types of resistive states: a low resistance state and a high resistance state. In the low resistance state, a filament 105 is formed within the resistance change film 102 so as to penetrate the resistance change film 102. This filament 105 becomes a current path. In the high resistance state, the filament 105 is separated or disappears within the resistance change film 102, and the current path is not constituted.

[0041] The lower electrode 101 is formed of a conductive film, for example, tungsten (W). The lower electrode 101 is provided on a top surface of the bit line BL and serves as a cathode of the memory cell MC. The resistance change film 102 is provided between the lower electrode 101 and the metal film 103, and formed of, for example, oxide such as silicon oxide (SiO.sub.2) or alumina (Al.sub.2O.sub.3), or nitride such as silicon nitride (Si.sub.3N.sub.4). The metal film 103 is provided between the resistance change film 102 and the upper electrode 104, and constituted of, for example, metal such as copper (Cu) or silver (Ag), or compound including one or more types of metallic element. As an example, the metal film 103 is described to be copper in the first embodiment. The metal film 103 supplies metal ions, which constitute the filament 105, into the resistance change film 102. The upper electrode 104 is formed of a conductive film, for example, tungsten (W). The upper electrode 104 is provided between the word line WL and the resistance change film 102 and serves as an anode of the memory cell MC. The filament 105 is made of metal ions such as copper ions (Cu.sup.+) or silver ions (Ag.sup.2+) supplied into the resistance change film 102 from the metal film 103.

[0042] FIG. 5 is a schematic diagram for describing a set operation that performs transition of the memory cell MC from the high resistance state to the low resistance state. In the set operation, a voltage of a polarity in which the upper electrode 104 (anode, the second electrode) has a higher potential and the lower electrode 101 (cathode, the first electrode) has a lower potential (hereinafter referred to as a "first polarity") is applied. This causes the copper included in the metal film 103 to become positive ions to move toward the lower electrode 101, which is a negative electrode. In this respect, the copper ions Cu.sup.+ diffuse in a direction of the lower electrode 101 through vacancies V within the resistance change film 102. Then, the copper ions Cu.sup.+ combines with silicon atoms, oxygen atoms or similar atoms within the resistance change film 102 to form the filament 105 within the resistance change film 102. This constitutes the current path within the resistance change film 102, and the memory cell MC becomes the low resistance state.

[0043] The vacancy V within the resistance change film 102 is a part where an atom is missing within a lattice in which oxygen atoms are accurately arranged. The vacancy Visa point defect, which occurs when a lattice of a material that constitutes the resistance change film 102 is destroyed, for example, due to an application of electric field to the resistance change film 102. The copper ion Cu.sup.+ has a large atomic size, therefore a barrier is high when moving between the lattices constituting the resistance change film 102. In view of this, the copper ion Cu.sup.+ needs electrically high energy to move between the lattices. Here, if the vacancy V and a crystal defect are present at the proximity of the copper ion Cu.sup.+, the copper ion Cu.sup.+ is allowed to move through the vacancy V, thus lowering the barrier between the lattices. In view of this, the diffusion speed of the copper ion Cu.sup.+ depends on the vacancy concentration. That is, by increasing the vacancy concentration, the diffusion of the copper ions Cu.sup.+ with a low electrical energy supply is achieved.

[0044] The larger the following diffusion coefficient D is, the easier the copper ion Cu.sup.+ moves.

D .varies. exp ( - E a - f ( V ) k B T ) Formula ( 1 ) ##EQU00001##

[0045] Ea: diffusion barrier (potential energy), f(V): variation amount of barrier height relative to electric field, k.sub.B: Boltzmann constant, T: temperature, and V: electric field.

[0046] A description of the above formula (1) will be given.

[0047] Diffusibility is determined by a diffusion barrier Ea, a variation amount f(V) of a barrier height relative to an electric field, and a temperature.

[0048] A description of the diffusion barrier Ea will be given. The copper ion Cu.sup.+ passes through a position where a distance between the lattices is narrow when the copper ion Cu.sup.+ is moving through a gap of the lattices. In this respect, the copper ion Cu.sup.+ proceeds by pushing away nearby atoms, therefore the diffusion barrier Ea is present between the lattices. Here, when the vacancy V is present in the peripheral area of the copper ion Cu.sup.+, a force needed to push away the nearby atoms decreases, therefore the diffusion barrier Ea between the lattices lowers.

[0049] A description of the variation amount f(V) of the barrier height relative to the electric field will be given. By applying the electric field V between the lower electrode 101 and the upper electrode 104, f(V) increases due to the occurrence of an electric force corresponding to the strength of the electric field V to the copper ion Cu.sup.+, and the barrier height Ea-f(V) in the electric field direction lowers. As described above, the vacancy V reduces the diffusion barrier Ea of the copper ion Cu.sup.+ to assist the diffusion of the copper ions Cu.sup.+. Here, the number of the vacancy V at the proximity of the lower electrode 101 increases corresponding to the direction and the strength of the applied electric field. Such reason also lowers the barrier height Ea-f(V) in the electric field direction, and the copper ion Cu.sup.+ diffuses easily within the resistance change film 102.

[0050] The absolute temperature T is a value indicating the Joule heat that is generated by a formation of the filament 105 within the resistance change film 102 causing a current flow within the resistance change film 102.

[0051] FIG. 6 is a schematic diagram for describing a reset operation that performs transition of the memory cell MC from the low resistance state to the high resistance state. In the reset operation, a voltage of an inverse polarity of the first polarity in which the lower electrode 101 (cathode) has a higher potential and the upper electrode 104 (anode) has a lower potential (hereinafter referred to as a "second polarity") is applied. This causes the copper included in the filament 105 to become positive ions to move toward the upper electrode 104, which is a negative electrode. In this respect, the copper ions Cu.sup.+ diffuse in a direction going away from the lower electrode 101 through the vacancies V within the resistance change film 102. This causes the filament 105 of the resistance change film 102 to be separated or disappear, and the current path disappears. Thus, the memory cell MC becomes the high resistance state.

[0052] FIG. 7 is a schematic graph illustrating current-voltage characteristics of the memory cell MC. The horizontal axis indicates a voltage V.sub.MC applied between the lower electrode 101 and the upper electrode 104 of the memory cell MC. The vertical axis indicates a current I.sub.MC flown to the memory cell MC along a logarithmic axis.

[0053] First, a case where the voltage V.sub.MC of the first polarity is applied to the memory cell MC in the high resistance state will be described. In the case where the voltage V.sub.MC is increased from 0 V, the filament 105 is formed within the resistance change film 102 when the voltage V.sub.MC becomes larger than a transition voltage V.sub.T, therefore the current I.sub.MC increases extremely. When the voltage V.sub.MC reaches a set voltage V.sub.SET, the memory cell MC transitions from the high resistance state to the low resistance state, and the current I.sub.MC is saturated. The filament 105 is maintained even the voltage V.sub.MC is reduced to 0 V in this state because there is no external force to diffuse the atoms. Thus, the low resistance state of the memory cell MC is maintained.

[0054] Next, a case where the voltage V.sub.MC of the second polarity is applied to the memory cell MC in the low resistance state will be described. In the case where the voltage V.sub.MC is increased, the filament 105 is separated or disappears when the voltage V.sub.MC reaches a reset voltage V.sub.RESET, therefore the memory cell MC transitions from the low resistance state to the high resistance state. The filament 105 is maintained to be in the separated or disappearing state even the voltage V.sub.MC is reduced to 0 V in this state, therefore the high resistance state is maintained. The current I.sub.MC hardly flows to the memory cell MC even the voltage V.sub.MC is applied to the second polarity of the memory cell MC.

[0055] When data is read from the memory cell MC, the voltage V.sub.MC is set to, for example, a reading voltage V.sub.READ. The reading voltage V.sub.READ is a voltage of the first polarity and smaller than the transition voltage V.sub.T. When the voltage V.sub.MC is the reading voltage V.sub.READ, the memory cell MC in the high resistance state only has a current smaller than a threshold I.sub.TH flown, and the memory cell MC in the low resistance state has a current larger than the threshold I.sub.TH flown.

[0056] [Operation]

[0057] FIG. 8 is a circuit diagram for describing an operation of the semiconductor memory device according to the embodiment. The following describes the cases where a set operation and a reset operation are performed to a selected memory cell MC.sub.S connected to a selected bit line BL.sub.S and a selected word line WL.sub.S.

[0058] [Set Operation]

[0059] FIG. 9 is a timing diagram for describing the set operation. FIG. 9 illustrates voltages applied to the selected word line WL.sub.S, the selected bit line BL.sub.S, the selected memory cell MC.sub.S, a non-selected word line WL.sub.U, and a non-selected bit line BL.sub.U.

[0060] At Timing T.sub.101, a selected bit line voltage V.sub.S.sub._.sub.BLS is applied to the selected bit line BL.sub.S, and an intermediate potential between the selected bit line voltage V.sub.S.sub._.sub.BLS and the selected word line voltage V.sub.S.sub._.sub.WLS, which will be described later, are applied to the selected word line WL.sub.S, the non-selected word line WL.sub.U, and the non-selected bit line BL.sub.U. The selected bit line voltage V.sub.S.sub._.sub.BLS is a negative voltage. The selected bit line voltage V.sub.S.sub._.sub.BLS is set to a magnitude with which a non-selected memory cell connected to the non-selected word line WL.sub.U and the selected bit line BL.sub.S does not transition to the low resistance state. By applying these voltages, a voltage of the first polarity |V.sub.S.sub._.sub.BLS| is applied to the selected memory cell MC.sub.S.

[0061] At Timing T.sub.102, the selected word line voltage V.sub.S.sub._.sub.WLS is applied to the selected word line WL.sub.S. The selected word line voltage V.sub.S.sub._.sub.WLS is a positive voltage. The selected word line voltage V.sub.S.sub._.sub.WLS is set to a magnitude with which the non-selected memory cell connected to the selected word line WL.sub.S and the non-selected bit line BL.sub.U does not transition to the low resistance state. By doing this, a writing pulse (third pulse) P3 is applied to the selected memory cell MC.sub.S. The voltage of the writing pulse P3 is the set voltage V.sub.SET, which has been described with reference to FIG. 7. This causes the copper ions Cu.sup.+ within the selected memory cell MC.sub.S to approach the lower electrode 101 through the vacancies V to transition the selected memory cell MC.sub.S to be in the low resistance state.

[0062] At Timing T.sub.103, the voltage of the selected word line WL.sub.S is set to 0 V. In other words, the application of the selected word line voltage V.sub.S.sub._.sub.WLS is terminated. By doing this, the voltage applied to the selected memory cell MC.sub.S becomes |V.sub.S.sub._.sub.BLS|.

[0063] At Timing T.sub.104, the voltage of the selected bit line BL.sub.S is set to 0 V. In other words, the application of the selected bit line voltage V.sub.S.sub._.sub.BLS is terminated. By doing this, the voltage applied to the selected memory cell MC.sub.S becomes 0 V.

[0064] [Reset Operation]

[0065] FIG. 10 is a timing diagram for describing the reset operation according to the embodiment. FIG. 10 illustrates voltages applied to the selected word line WL.sub.S, the selected bit line BL.sub.S, the selected memory cell MC.sub.S, the non-selected word line WL.sub.U, and the non-selected bit line BL.sub.U.

[0066] At Timing T.sub.201, a selected bit line voltage V.sub.R.sub._.sub.BLS1 (third voltage) is applied to the selected bit line BL.sub.S, and an intermediate potential between a selected bit line voltage V.sub.R.sub._.sub.BLS2, which will be described later, and the selected word line voltage V.sub.R.sub._.sub.WLS2, which will be described later, are applied to the selected word line WL.sub.S, the non-selected word line WL.sub.U, and the non-selected bit line BL.sub.U. The selected bit line voltage V.sub.R.sub._.sub.BLS1 is a negative voltage. The selected bit line voltage V.sub.R.sub._.sub.BLS1 is set to a magnitude with which the non-selected memory cell connected to the non-selected word line WL.sub.U and the selected bit line BL.sub.S does not transition to the low resistance state. By applying these voltages, a voltage of the first polarity |V.sub.R.sub._.sub.BLS1| is applied to the selected memory cell MC.sub.S.

[0067] At Timing T.sub.202, a selected word line voltage V.sub.R.sub._.sub.WLS1 (first voltage) is applied to the selected word line WL.sub.S. The selected word line voltage V.sub.R.sub._.sub.WLS1 is a positive voltage. The selected word line voltage V.sub.R.sub._.sub.WLS1 is set to, for example, a magnitude with which the non-selected memory cell connected to the selected word line WL.sub.S and the non-selected bit line BL.sub.U does not transition to the low resistance state. By doing this, the first pulse P1 is applied to the selected memory cell MC.sub.S. The first pulse P1 includes a voltage V.sub.P1 of the first polarity. This causes the current flow in the selected memory cell MC.sub.S to generate the Joule heat, for example. The vacancies V within the selected memory cell MC.sub.S are attracted to the lower electrode 101 to increase the concentration of the vacancies V at the proximity of the lower electrode 101. The voltage V.sub.P1, for example, has a magnitude of equal to or more than 30% and equal to or less than 80% of the third pulse set voltage V.sub.SET (FIG. 9).

[0068] At Timing T.sub.203, the voltage of the selected word line WL.sub.S is reduced to the intermediate potential between the selected bit line voltage V.sub.R.sub._.sub.BLS2 and the selected word line voltage V.sub.R.sub._.sub.WLS2. In other words, the application of the selected word line voltage V.sub.R.sub._.sub.BLS1 is terminated. By doing this, the voltage applied to the selected memory cell MC.sub.S becomes |V.sub.R.sub._.sub.BLS1|.

[0069] At Timing T.sub.204, the selected bit line voltage V.sub.R.sub._.sub.BLS2 (fourth voltage) is applied to the selected bit line BL.sub.S. The selected bit line voltage V.sub.R.sub._.sub.BLS2 is a positive voltage. The selected bit line voltage V.sub.R.sub._.sub.BLS2 is set to a magnitude with which the non-selected memory cell connected to the non-selected word line WL.sub.U and the selected bit line BL.sub.S does not transition to the high resistance state. By doing this, a voltage V.sub.R.sub._.sub.BLS2 of the second polarity is applied the selected memory cell MC.sub.S.

[0070] At Timing T.sub.205, the selected word line voltage V.sub.R.sub._.sub.WLS2 (second voltage) is applied to the selected word line WL.sub.S. The selected word line voltage V.sub.R.sub._.sub.WLS2 is a negative voltage. The selected word line voltage V.sub.R.sub._.sub.WLS2 is set to a magnitude with which the non-selected memory cell connected to the selected word line WL.sub.S and the non-selected bit line BL.sub.U does not transition to the high resistance state. By doing this, the second pulse P2 is applied to the selected memory cell MC.sub.S. The voltage of the second pulse P2 is a reset voltage V.sub.RESET (FIG. 7) that has the second polarity. This causes the copper ions Cu.sup.+ within the selected memory cell MC.sub.S to separate from the lower electrode 101 through the vacancies V to cause the selected memory cell MC.sub.S to be the high resistance state.

[0071] At Timing T.sub.206, the voltage of the selected word line WL.sub.S is increased to the intermediate potential between the selected bit line voltage V.sub.R.sub._.sub.BLS2 and the selected word line voltage V.sub.R.sub._.sub.WLS2. In other words, the application of the selected word line voltage V.sub.R.sub._.sub.BLS2 is terminated. By doing this, the voltage applied to the selected memory cell MC.sub.S becomes V.sub.R.sub._.sub.BLS2.

[0072] At Timing T.sub.207, the voltage of the selected bit line BL.sub.S is reduced to the intermediate potential between the selected bit line voltage V.sub.R.sub._.sub.BLS2 and the selected word line voltage V.sub.R.sub._.sub.WLS2. In other words, the application of the selected bit line voltage V.sub.R.sub._.sub.BLS2 is terminated. By doing this, the voltage applied to the selected memory cell MC.sub.S becomes 0 V.

[0073] [Effect]

[0074] FIG. 11 is a timing diagram for describing a reset operation according to a comparative example. FIG. 11 illustrates voltages applied to the selected word line WL.sub.S, the selected bit line BL.sub.S, the selected memory cell MC.sub.S, the non-selected word line WL.sub.U, and the non-selected bit line BL.sub.U. In the following description, a part similar to FIG. 10 is attached with an identical reference numeral and its explanation is omitted.

[0075] In the reset operation according to the comparative example, the negative selected bit line voltage V.sub.R.sub._.sub.BLS1 (third voltage) is not applied to the selected bit line BL.sub.S, and the positive selected word line voltage V.sub.R.sub._.sub.WLS1 (first voltage) is not applied to the selected word line WL.sub.S. Accordingly, the selected memory cell MC.sub.S is not applied with the first pulse P1 of the first polarity.

[0076] As described above, even the voltage of the second polarity is applied to the memory cell MC, the current does not flow. In other words, in order to increase the temperature T by heating the filament 105 with the Joule heat, the voltage of the first polarity needs to be applied. Accordingly, in the comparative example, the current does not flow to the selected memory cell MC.sub.S and the Joule heat is not generated. Additionally, in the comparative example, the vacancy concentration at the proximity of the lower electrode 101 is relatively low. In such an aspect, a phenomenon where the selected memory cell MC.sub.S does not transition to the high resistance state (reset failure) sometimes occurs in spite of applying the reset voltage V.sub.RESET of the second polarity to the selected memory cell MC.sub.S.

[0077] Therefore, in the reset operation according the embodiment, as described with reference to FIG. 10, the first pulse P1 having the voltage of the first polarity is applied before the second pulse P2 having the voltage of the second polarity is applied. Accordingly, the current is flown to the selected memory cell MC.sub.S before the second pulse P2 is applied to generate the Joule heat and to increase the diffusion coefficient D of the copper ion Cu.sup.+, thus accelerating the diffusion speed of the copper ion Cu.sup.+. This reduces the occurrence of the reset failure to ensure the selected memory cell MC.sub.S transitioning to the high resistance state preferably.

[0078] Additionally, applying the first pulse P1 having the voltage of the first polarity ensures the facilitated move of the copper ion Cu.sup.+ by increasing the concentration of the vacancy V at the proximity of the lower electrode 101 that significantly contribute to the disappearance of the current path to increase the number of sites where the copper ion Cu.sup.+ is movable. This reduces the occurrence of the reset failure to ensure the selected memory cell MC.sub.S transitioning to the high resistance state preferably.

[0079] Note that, in the reset operation, the copper ion Cu.sup.+ is moved to a direction separating from the lower electrode 101. Accordingly, at least, the total amount of the copper ions Cu.sup.+ that move to a direction approaching the lower electrode 101 is less than the total amount of the copper ions Cu.sup.+ that move to the direction separating from the lower electrode 101. Accordingly, the product of an amplitude (voltage V.sub.P1) and a pulse width t.sub.p1 of the first pulse P1 is less than the product of an amplitude (reset voltage V.sub.RESET) and a pulse width t.sub.p3 of the second pulse P2.

[0080] In order to perform the reset operation using the Joule heat and the vacancy V, it is preferable that the second pulse P2 is applied immediately after the first pulse P1 is applied to form the filament 105 and generate the Joule heat. For example, a time t.sub.p2 from the end of the first pulse P1 application to the start of the second pulse P2 application may be within 100 nsec.

Second Embodiment

[0081] FIG. 12 is a timing diagram for describing the reset operation according to a second embodiment. FIG. 12 illustrates voltages applied to the selected word line WL.sub.S, the selected bit line BL.sub.S, the selected memory cell MC.sub.S, the non-selected word line WL.sub.U, and the non-selected bit line BL.sub.U. in the following description, a part similar to the first embodiment is attached with an identical reference numeral and its explanation is omitted.

[0082] As described with reference to FIG. 10, in the reset operation according to the first embodiment, the intermediate potential between the selected bit line voltage V.sub.R.sub._.sub.BLS2 and the selected word line voltage V.sub.R.sub._.sub.WLS2 is approximately 0 V, and a negative voltage is applied to the selected bit line BL.sub.S and the selected word line WL.sub.S. On the other hand, according to the embodiment, as illustrated in FIG. 12, an intermediate potential between the selected bit line voltage (V.sub.0) and the selected word line voltage V.sub.R.sub._.sub.WLS2' is a positive voltage, and the negative voltage is not applied to the selected word line WL.sub.S, the selected bit line BL.sub.S, the non-selected word line WL.sub.U, and the non-selected bit line BL.sub.U.

[0083] At Timing T.sub.301, the voltage V.sub.0 is applied to the selected word line WL.sub.S, the selected bit line BL.sub.S, and the non-selected word line WL.sub.U. The non-selected bit line voltage V.sub.R.sub._.sub.BLU1 (fifth voltage) is applied to the non-selected bit line BL.sub.U. The voltage V.sub.0 is the positive voltage. The non-selected bit line voltage V.sub.R.sub._.sub.BLU1 is a positive voltage larger than the voltage V.sub.0, and is set to a magnitude with which the non-selected memory cell connected to the non-selected bit line BL.sub.U does not transition to the low resistance state.

[0084] At Timing T.sub.302, the selected word line voltage V.sub.R.sub._.sub.WLS1' (first voltage) is applied to the selected word line WL.sub.S. The selected word line voltage V.sub.R.sub._.sub.WLS1' is a positive voltage larger than the voltage V.sub.0. By doing this, the first pulse P1 is applied to the selected memory cell MC.sub.S.

[0085] At Timing T.sub.303, the voltage of the selected word line WL.sub.S is reduced to V.sub.0. By doing this, the voltage applied to the selected memory cell MC.sub.S becomes 0 V.

[0086] At Timing T.sub.304, the voltage of the non-selected bit line BL.sub.U is reduced to the non-selected bit line voltage V.sub.R.sub._.sub.BLU2 (sixth voltage) from the non-selected bit line voltage V.sub.R.sub._.sub.BLU1 (fifth voltage). The non-selected bit line voltage V.sub.R.sub._.sub.BLU2 is a positive voltage smaller than the non-selected bit line voltage V.sub.R.sub._.sub.BLU1 and the voltage V.sub.0. The non-selected bit line voltage V.sub.R.sub._.sub.BLU2 is set to a magnitude with which the non-selected memory cell connected to the non-selected word line WL.sub.U and the non-selected bit line BL.sub.U does not transition to the low resistance state.

[0087] At Timing T.sub.305, the selected word line voltage V.sub.R.sub._.sub.WLS2' (second voltage) is applied to the selected word line WL.sub.S. The selected word line voltage V.sub.R.sub._.sub.WLS2' is a voltage lower than the voltage V.sub.0 and the non-selected bit line voltage V.sub.R.sub._.sub.BLU2. The selected word line voltage V.sub.R.sub._.sub.WLS2' is set such that the difference between the voltage V.sub.0 and the selected word line voltage V.sub.R.sub._.sub.WLS2 is the reset voltage V.sub.RESET (FIG. 7). The selected word line voltage V.sub.R.sub._.sub.WLS2 is set to a magnitude with which the non-selected memory cell connected to the selected word line WL.sub.S and the non-selected bit line BL.sub.U does not transition to the high resistance state. In the example illustrated in FIG. 12, the selected word line voltage V.sub.R.sub._.sub.WLS2' is 0 V. By doing this, the second pulse P2 is applied to the selected memory cell MC.sub.S.

[0088] At Timing T.sub.306, the voltage of the selected word line WL.sub.S is increased to V.sub.0. By doing this, the voltage applied to the selected memory cell MC.sub.S becomes 0 V.

[0089] At Timing T.sub.307, the voltages of the selected word line WL.sub.S, the selected bit line BL.sub.S, the non-selected word line WL.sub.U, and the non-selected bit line BL.sub.U are reduced to 0 V.

Third Embodiment

[0090] [Set Operation]

[0091] FIG. 13 is a flowchart for describing a set operation according to a third embodiment. FIG. 14 is a timing diagram for describing the set operation. In the following description, a part similar to the first embodiment is attached with an identical reference numeral and its explanation is omitted.

[0092] As described with reference to FIG. 9, in the set operation according to the first embodiment, the voltage V.sub.SET of the writing pulse (third pulse) P3 has a constant magnitude.

[0093] On the other hand, in the third embodiment, as illustrated in FIG. 13 and FIG. 14, the writing pulse (fourth pulse) P4 is applied to the selected memory cell MC.sub.S for several times, and every time the application of the writing pulse P4 is terminated, a verify operation is performed to confirm whether the selected memory cell MC.sub.S is in a desired state or not. The set operation is terminated at the point when the selected memory cell MC.sub.S is in the desired state. The voltage V.sub.P4 of the writing pulse (fourth pulse) P4 is increased. In the examples illustrated in FIG. 13 and FIG. 14, the desired state is the low resistance state.

[0094] At Step S101, the writing pulse P4 is applied to the selected memory cell MC.sub.S. The voltage V.sub.P4 of the writing pulse P4 is the voltage of the first polarity.

[0095] At Step S102, the verify operation is performed. In the verify operation, as illustrated in FIG. 14, a fifth pulse P5 is applied to the selected memory cell MC.sub.S, and whether the selected memory cell MC.sub.S is transitioned to the low resistance state or not is confirmed. The fifth pulse P5 has a voltage of approximately the reading voltage V.sub.READ (FIG. 7), for example. At Step S102, when the memory cell MC is transitioned to the low resistance state, the set operation is terminated. When the memory cell MC is not transitioned to the low resistance state, Step S103 is performed.

[0096] At Step S103, the voltage V.sub.P4 of the writing pulse P4 is increased. After Step S103 is performed, Step S101 and Step S102 are performed again. Accordingly, as illustrated in FIG. 14, the voltage V.sub.P4 of the writing pulse P4 increases.

[0097] [Reset Operation]

[0098] The reset operation according to the embodiment is performed similarly to the first or the second embodiment. However, according to the embodiment, a magnitude of the voltage V.sub.P1 of the first pulse P1 (FIG. 10 and FIG. 12) is, for example, the magnitude that is equal to or more than 80% of an initial value of the voltage V.sub.P4 of the writing pulse P4.

Fourth Embodiment

[0099] FIG. 15 is a flowchart for describing a reset operation according to a fourth embodiment. FIG. 16 is a timing diagram for describing the reset operation. In the following description, apart similar to the first embodiment is attached with an identical reference numeral and its explanation is omitted.

[0100] As described with reference to FIG. 10, in the reset operation according to the first embodiment, the voltage V.sub.RESET of the second pulse P2 has a constant magnitude.

[0101] On the other hand, in the fourth embodiment, as illustrated in FIG. 15 and FIG. 16, the selected memory cell MC.sub.S is applied with the first pulse P1 and the second pulse P2' for several times, and every time the application of the second pulse P2' is terminated, the verify operation is performed to confirm whether the selected memory cell MC.sub.S is in a desired state or not. The reset operation is terminated at the point when the selected memory cell MC.sub.S is in the desired state. The magnitude of the voltage V.sub.P2 of the second pulse P2' is increased. In the examples illustrated in FIG. 15 and FIG. 16, the desired state is the high resistance state.

[0102] At Step S201, the first pulse P1 and the second pulse P2' is applied to the selected memory cell MC.sub.S. The second pulse P2' has the voltage of the second polarity. The voltage V.sub.P2 of the second pulse P2' is smaller than the reset voltage V.sub.RESET at a phase of the initial value.

[0103] At Step S202, the verify operation is performed. In the verify operation, as illustrated in FIG. 16, the fifth pulse P5 is applied to the selected memory cell MC.sub.S, and whether the selected memory cell MC.sub.S is transitioned to the high resistance state or not is confirmed. At Step S202, when the memory cell MC is transitioned to the high resistance state, the reset operation is terminated. When the memory cell MC is not transitioned to the high resistance state, Step S203 is performed.

[0104] At Step S203, the voltage V.sub.P2 of the second pulse P2' is increased. After performing step S203, step S201 and step S202 are performed again. Accordingly, the magnitude of the voltage V.sub.P2 of the second pulse P2' increases as illustrated in FIG. 16. The second pulse P2' having a voltage value amplified in such a manner may be referred to as a sixth pulse P6.

[0105] [Others]

[0106] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms: furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

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