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United States Patent Application 
20180115329

Kind Code

A1

LI; Liangbin
; et al.

April 26, 2018

EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR
Abstract
Apparatuses (and methods of manufacturing same), systems, and methods
concerning polyphase digital filters are described. In one aspect, an
apparatus is provided, including at least one pair of subfilters, each
having symmetric coefficients, and a lattice comprising two adders and
feedlines corresponding to each of the at least one pair of subfilters,
each having symmetric coefficients. In one aspect, the apparatus is a
polyphase finite impulse response (FIR) digital filter, including an
interpolator and a decimator, where each of the interpolator and the
decimator have at least one pair of subfilters, each having symmetric
coefficients, and a lattice comprising two adders and feedlines
corresponding to each of the at least one pair of subfilters, each having
symmetric coefficients.
Inventors: 
LI; Liangbin; (San Diego, CA)
; DAYAL; Pranav; (San Diego, CA)
; LEE; Jungwon; (San Diego, CA)
; FEYGIN; Gennady; (San Diego, CA)

Applicant:  Name  City  State  Country  Type  Samsung Electronics Co., Ltd.  Gyeonggido  
KR   
Assignee: 
Samsung Electronics Co., Ltd.

Family ID:

1000002463253

Appl. No.:

15/402651

Filed:

January 10, 2017 
Related U.S. Patent Documents
      
 Application Number  Filing Date  Patent Number 

 62412452  Oct 25, 2016  

Current U.S. Class: 
1/1 
Current CPC Class: 
H04B 1/0042 20130101; H04B 3/462 20130101; H04B 1/0046 20130101 
International Class: 
H04B 1/00 20060101 H04B001/00; H04B 3/462 20060101 H04B003/462 
Claims
1. An apparatus, comprising: at least one pair of subfilters, each having
symmetric coefficients; and a lattice comprising two adders and feedlines
corresponding to each of the at least one pair of subfilters, wherein the
symmetric coefficients of each of the at least one pair of subfilters are
transformed from an initial pair of antisymmetric coefficients h.sub.m
and h.sub.Rm, R being a total number of subfilters, and m being a
subfilter index, where m=1, 2, . . . , R.
2. The apparatus of claim 1, wherein the apparatus comprises a polyphase
finite impulse response (FIR) digital filter.
3. The apparatus of claim 1, wherein the apparatus comprises a polyphase
Nyquist digital filter.
4. (canceled)
5. The apparatus of claim 1, further comprising: an interpolator
comprising the at least one pair of subfilters and the lattice.
6. The apparatus of claim 5, wherein the interpolator further comprises:
a subfilter whose coefficients are symmetric, wherein tap outputs in the
subfilter having the same coefficient are added together before being
multiplied by the coefficient.
7. The apparatus of claim 5, wherein the two adders of the lattice for
each pair of subfilters in the interpolator comprise: a first adder which
adds outputs of the two subfilters together; and a second adder which
adds an output of one subfilter to the negative value of an output of the
other subfilter.
8. (canceled)
9. The apparatus of claim 5, wherein: one of each pair of subfilters has
a first coefficient function: ( h m + h R  m 2 ) ;
##EQU00029## and the other of each pair of subfilters has a second
coefficient function: ( h m  h R  m 2 ) ##EQU00030##
wherein, when the input to each subfilter is x, the outputs of the pair
of subfilters are x * ( h m + h R  m 2 ) ; and x
* ( h m  h R  m 2 ) , ##EQU00031## respectively.
10. The apparatus of claim 9, wherein the two adders of the lattice
comprise: a first adder which adds x * ( h m + h R  m 2 )
and x * ( h m  h R  m 2 ) , ##EQU00032## to
output x * h m = x * ( h m + h R  m 2 ) + x * (
h m  h R  m 2 ) ; ##EQU00033## and a second adder which
adds x * ( h m + h R  m 2 ) ##EQU00034## and the negative
value of x * ( h m  h R  m 2 ) , ##EQU00035## to output
x * h ( R  m ) = x * ( h m + h R  m 2 )  x *
( h m  h R  m 2 ) . ##EQU00036##
11. The apparatus of claim 1, further comprising: a decimator comprising
the at least one pair of subfilters and the lattice.
12. The apparatus of claim 11, wherein the decimator further comprises: a
serialtoparallel (S2P) converter which receives serial output and
converts it to parallel output.
13. The apparatus of claim 12, wherein the two adders of the lattice for
each pair of subfilters in the decimator receive the parallel output of
the S2P converter.
14. The apparatus of claim 11, wherein the decimator comprises: a
subfilter whose coefficients are symmetric, wherein tap outputs in the
subfilter having the same coefficient are added together before being
multiplied by the coefficient.
15. (canceled)
16. The apparatus of claim 11, wherein: one of the pair of subfilters has
a first coefficient function: ( h m + h R  m 2 ) ;
##EQU00037## and the other has a second coefficient function: ( h m
 h R  m 2 ) . ##EQU00038##
17. An apparatus having a polyphase architecture for sampling rate
conversion, comprising: a lattice comprising one or more sets of adders
and feedlines; and at least one group of subfilters, where each group of
subfilters has a corresponding one of the one or more sets of adders and
feedlines, wherein coefficients of subfilters in each group of subfilters
are generated from coefficients in an initial set of coefficients, where
the coefficients in the initial set of coefficients exhibit antisymmetric
pair properties, and wherein each group of subfilters and its
corresponding set of adders and feedlines generate the same overall
output as subfilters having the coefficients from the initial set of
coefficients.
18. The apparatus of claim 17, wherein the apparatus is a finite impulse
response (FIR) digital filter.
19. The apparatus of claim 18, further comprising: an interpolator
comprising the lattice and the at least one group of subfilters, wherein
the output of each group of subfilters feeds the adders in its
corresponding set of adders and feedlines.
20. The apparatus of claim 18, further comprising: a decimator comprising
the lattice and the at least one group of subfilters, wherein the input
of each group of subfilters is fed by the adders in its corresponding set
of adders and feedlines.
21. A method of manufacturing a polyphase apparatus for sampling rate
conversion, comprising: manufacturing a component of the polyphase
apparatus comprising: at least one pair of subfilters, each having
symmetric coefficients; and a lattice comprising two adders and feedlines
corresponding to each of the at least one pair of subfilters, wherein the
symmetric coefficients of each of the at least one pair of subfilters are
transformed from an initial pair of antisymmetric coefficients h.sub.m
and h.sub.Rm, R being a total number of subfilters, and in being a
subfilter index, where m=1, 2, . . . R.
22. The method of claim 21, wherein the component comprises an
interpolator, and wherein the output of each pair of subfilters feeds its
corresponding two adders and feedlines.
23. The method of claim 22, wherein manufacturing the interpolator
comprises: manufacturing the two adders of the lattice for each pair of
subfilters such that one adder adds the outputs of the two subfilters
together and the other adder adds the output of one subfilter to the
negative value of the output of the other subfilter.
24. The method of claim 23, wherein manufacturing the interpolator
comprises: manufacturing a paralleltoserial (P2S) converter which
receives the output of the adders.
25. The method of claim 21, wherein the component comprises a decimator,
and wherein the input of each pair of subfilters is fed by its
corresponding two adders.
26. The method of claim 25, wherein manufacturing the decimator
comprises: manufacturing a serialtoparallel (S2P) converter.
27. The method of claim 26, wherein manufacturing the decimator
comprises: manufacturing the two adders of the lattice for each pair of
subfilters to receive the parallel output of the S2P converter.
28. A method of testing a polyphase apparatus for sampling rate
conversion, comprising: testing whether the polyphase apparatus has a
component comprising: at least one pair of subfilters, each having
symmetric coefficients; and a lattice comprising two adders and feedlines
corresponding to each of the at least one symmetric pair of subfilters;
testing whether the symmetric coefficients of each pair of subfilters are
transformed from an initial pair of antisymmetric coefficients h.sub.m
and h.sub.Rm, R being a total number of subfilters and m being a
subfilter index, where m=1, 2, . . . , R; testing whether one of the pair
of subfilters has a first coefficient function: ( h m + h R  m
2 ) ; ##EQU00039## and testing whether the other has a second
coefficient function: ( h m  h R  m 2 ) . ##EQU00040##
29. (canceled)
30. (canceled)
31. The apparatus of claim 17, wherein each group of subfilters comprises
a pair of subfilters.
Description
PRIORITY
[0001] This application claims priority under 35 U.S.C. .sctn. 119(e) to
U.S. Prov. Pat. App. Ser. No. 62/412,452 filed on Oct. 25, 2016 in the
U.S. Patent and Trademark Office, the entire contents of which are
incorporated herein by reference.
FIELD
[0002] The present disclosure relates generally to multirate digital
filters, filter banks, and signal processing, and more particularly, to a
polyphase architecture for an interpolator and a decimator.
BACKGROUND
[0003] Multirate digital filters are used in telecommunications, speech
processing, image compression, antenna/radar systems, spectrum analysis,
and in the wide myriad of applications and functions in the growing
Internet of Things (IoT). "Multirate" literally means "multiple rates,"
i.e., that there are multiple sampling rates being used in the system.
[0004] The basic building blocks of a multirate digital system are
interpolation filters or interpolators, which increase the sampling rate
of an input digital signal, and decimations filters or decimators, which
decrease the sampling rate of an input digital signal.
SUMMARY
[0005] Accordingly, the present disclosure aims at addressing at least the
problems and/or disadvantages described herein and to provide at least
the advantages described below.
[0006] According to an aspect of the present disclosure, an apparatus is
provided, including at least one pair of subfilters, each having
symmetric coefficients, and a lattice comprising two adders and feedlines
corresponding to each of the at least one pair of subfilters, each having
symmetric coefficients.
[0007] According to an aspect of the present disclosure, an apparatus
having a polyphase architecture for sampling rate conversion is provided,
including a lattice comprising one or more sets of adders and feedlines
and at least one group of subfilters, where each group of subfilters has
a corresponding one of the one or more sets of adders and feedlines
comprising the lattice, wherein coefficients of subfilters in each group
of subfilters are generated from coefficients in an initial set of
coefficients, where the coefficients in an initial set of coefficients
exhibit antisymmetric pair properties, and wherein each group of
subfilters and its corresponding set of adders and feedlines generate the
same overall output as subfilters having the coefficients from the
initial set of coefficients.
[0008] According to an aspect of the present disclosure, a method of
manufacturing a polyphase apparatus for sampling rate conversion is
provided, including manufacturing a component of the polyphase apparatus
which includes at least one pair of subfilters, each having symmetric
coefficients, and a lattice comprising two adders and feedlines
corresponding to each of the at least one pair of subfilters, each having
symmetric coefficients.
[0009] According to an aspect of the present disclosure, a method of
testing a polyphase apparatus for sampling rate conversion is provided,
including testing whether the polyphase apparatus has a component which
includes at least one pair of subfilters, each having symmetric
coefficients, and a lattice comprising two adders and feedlines
corresponding to each of the at least one pair of subfilters, each having
symmetric coefficients.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The above and other aspects, features, and advantages of certain
embodiments of the present disclosure will be more apparent from the
following detailed description, taken in conjunction with the
accompanying drawings, in which:
[0011] FIGS. 1 and 2 are block diagrams of an interpolator and a
decimator, respectively, in a multirate digital sampling system;
[0012] FIGS. 3 and 4 are block diagrams of an interpolator and a
decimator, respectively, in a polyphase architecture of a multirate
digital sampling system;
[0013] FIG. 5 is block diagram of the function h.sub.1 performed by
subfilter1 in FIG. 4;
[0014] FIG. 6 is a block diagram of the function h.sub.1 performed by
subfilter1 in FIG. 4 with a simplified architecture using the symmetry of
the coefficients;
[0015] FIG. 7 is block diagram of the function h.sub.1 performed by
subfilter1 in FIG. 4, where the coefficients have an odd symmetry;
[0016] FIG. 8 is a block diagram of the function h.sub.1 performed by
subfilter1 in FIG. 4 with a simplified architecture using the odd
symmetry of the coefficients;
[0017] FIG. 9 is a block diagram of the general structure for pairs of
subfilters having antisymmetric coefficients, according to an embodiment
of the present disclosure;
[0018] FIGS. 10 and 11 are block diagrams of an interpolator and a
decimator, respectively, in a polyphase architecture of a multirate
digital sampling system, according to an embodiment of the present
disclosure;
[0019] FIGS. 12 and 13 show simulation results regarding multiplication
complexity and addition complexity, respectively, of conventional vs.
digital filter systems according to an embodiment of the present
disclosure; and
[0020] FIGS. 14 and 15 show examples of lattice implementations/structures
according to other embodiments of the present disclosure.
DETAILED DESCRIPTION
[0021] Hereinafter, embodiments of the present disclosure are described in
detail with reference to the accompanying drawings. It should be noted
that the same elements are designated by the same reference numerals
although they are shown in different drawings. In the following
description, specific details such as detailed configurations and
components are merely provided to assist in the overall understanding of
the embodiments of the present disclosure. Therefore, it should be
apparent to those skilled in the art that various changes and
modifications of the embodiments described herein may be made without
departing from the scope of the present disclosure. In addition,
descriptions of wellknown functions and constructions are omitted for
clarity and conciseness. The terms described below are terms defined in
consideration of the functions in the present disclosure, and may be
different according to users, intentions of the users, or customs.
Therefore, the definitions of the terms should be determined based on the
contents throughout the specification.
[0022] The present disclosure may have various modifications and various
embodiments, among which embodiments are described below in detail with
reference to the accompanying drawings. However, it should be understood
that the present disclosure is not limited to the embodiments, but
includes all modifications, equivalents, and alternatives within the
scope of the present disclosure.
[0023] Although terms including an ordinal number such as first and second
may be used for describing various elements, the structural elements are
not restricted by the terms. The terms are only used to distinguish one
element from another element. For example, without departing from the
scope of the present disclosure, a first structural element may be
referred to as a second structural element. Similarly, the second
structural element may also be referred to as the first structural
element. As used herein, the term "and/or" includes any and all
combinations of one or more associated items.
[0024] The terms used herein are merely used to describe various
embodiments of the present disclosure but are not intended to limit the
present disclosure. Singular forms are intended to include plural forms
unless the context clearly indicates otherwise. In the present
disclosure, it should be understood that the terms "include" or "have"
indicate existence of a feature, a number, a step, an operation, a
structural element, parts, or a combination thereof, and do not exclude
the existence or probability of addition of one or more other features,
numerals, steps, operations, structural elements, parts, or combinations
thereof.
[0025] Unless defined differently, all terms used herein have the same
meanings as those understood by a person skilled in the art to which the
present disclosure belongs. Such terms as those defined in a generally
used dictionary are to be interpreted to have the same meanings as the
contextual meanings in the relevant field of art, and are not to be
interpreted to have ideal or excessively formal meanings unless clearly
defined in the present disclosure.
[0026] Various embodiments may include one or more elements. An element
may include any structure arranged to perform certain operations.
Although an embodiment may be described with a limited number of elements
in a certain arrangement by way of example, the embodiment may include
more or less elements in alternate arrangements as desired for a given
implementation. It is worthy to note that any reference to "one
embodiment" or "an embodiment" means that a particular feature,
structure, or characteristic described in connection with the embodiment
is included in at least one embodiment. The appearance of the phrase "one
embodiment" (or "an embodiment") in various places in this specification
do not necessarily refer to the same embodiment.
[0027] FIG. 1 shows an interpolator 110 which receives N samples as input,
upsamples the input by R, and outputs RN samples. FIG. 2 shows a
decimator 120 receives the RN samples as input, downsamples by R, and
outputs N samples.
[0028] More specifically, the interpolator 110 upsamples by R, then
applies imaging filter 115 to remove the extra images created by the
upsampling before outputting the RN samples. The decimator 120 applies an
antialiasing filter 125 to an input RN samples to eliminate aliasing
(the overlap of shifted versions of a signal) and/or outofband noise,
and then downsamples by R to produce N samples as output.
[0029] The digital filters described above can be implemented using a
finite impulse response (FIR) filter at high sampling rates. Polyphase
decomposition can be used on such an FIR filter to decompose the FIR into
R groups, which results in a polyphase architecture using R subfilters,
thereby reducing the sampling rate per subfilter, thus reducing the
number of computations that need to be made during processing.
[0030] More specifically, polyphase decomposition results in an
interpolator and decimator as shown in FIGS. 3 and 4, respectively.
[0031] As shown in FIG. 3, the polyphase decomposition results in an
interpolator 210 with an input of N samples which are received by a
matching set of Subfilters 1 to R 213 performing functions h1 to hR,
respectively. The parallel outputs of Subfilters 1 to R 213 are input
into paralleltoserial converter (P2S) 217 which outputs a serial stream
of RN samples.
[0032] As shown in FIG. 4, the polyphase decomposition results in an
decimator 220 with an input of a serial stream of RN samples which are
received by a serialtoparallel converter (S2P) 227. The S2P 227 outputs
R parallel streams of N samples to a matching set of Subfilters 1 to R
223 performing functions h1 to hR, respectively. The parallel outputs of
Subfilters 1 to R 213 are added together to generate an output of N
samples.
[0033] The polyphase decomposition and resulting polyphase architecture of
each subfilter are described generally below.
[0034] The Z domain representation of the long FIR filter having
coefficients [g.sub.0, g.sub.1, g.sub.2, g.sub.3, . . . , g.sub.K] can be
written as Equation (1):
H ( Z ) = k = 0 : K g k Z  k ( 1 )
##EQU00001##
[0035] When K=MR1 for some integer M, the FIR filter can be
rewrittenor decomposedinto Equation (2).
H ( Z ) = m = 0 : R  1 ( g m + g R + m
Z  R + g 2 R + m Z  2 R + + g ( M  1
) R + m Z  ( M  1 ) R ) Z  m ( 2 )
##EQU00002##
[0036] As shown in Equation (2), the partial coefficients g within the
parentheses are linear combination of Z.sup.kR for some integer k. Thus,
the partial coefficients g for each value of m make one subfilter for the
decimator, as shown by Equations (3)(a)3(c) below:
h 1 = [ g 1 , g R + 1 , g 2 R + 1 , , g K
( M  1 ) R + 1 ] ( 3 ) ( a ) h 2 = [
g 2 , g R + 2 , g 2 R + 2 , , g K ( M  1 )
R + 2 ] ( 3 ) ( b ) h R = [ g 0 ,
g R , g 2 R , , g K ( M  1 ) R ] ( 3 )
( c ) ##EQU00003##
[0037] Here, each of the R subfilters has M taps, as will be discussed
further in reference to FIGS. 58 below.
[0038] In embodiments of the present disclosure, the finite impulse
response (FIR) filter underlying the polyphase decomposition/architecture
is a Nyquist filter (an Nth band filter) which further simplifies the
computations. In a Nyquist filter, K=MR where M is even. The Nyquist
filter with ratio R needs to satisfy the condition shown as a timedomain
representation in Equation (4).
g Rk = 0 , for all k except k = K
2 R ( 4 ) ##EQU00004##
[0039] This translates to the frequency domain definition of a Nyquist
filter as Equation (5).
k = 0 : R  1 H ( f F s  k R ) = c
e  j 2 .pi. fK F s 2 ( 5 )
##EQU00005##
where F.sub.s is the sampling rate of the digital filter and c denotes a
constant. The phase ramp
e  j 2 .pi. fK F s 2 ##EQU00006##
is based on the assumption that the filter design is causal. The Nyquist
filter preserves not only the linear phase property (i.e., inband output
signals are delayed versions of inband input signals), but also the last
subfilter h.sub.R always has an impulse as the response of the filter.
Moreover, when R is even, one subfilter has symmetric coefficients, which
allows for further reductions in computations.
[0040] For example, when R=2, the Nyquist filter becomes a halfband filter
(HBF), where the coefficients of the underlying FIR are shown in Equation
(6).
G.sub.R=2=[g.sub.1,0,g.sub.3,0, . . . g.sub.2n+1,1,g.sub.2n+1, . . .
,0,g.sub.3,0,g.sub.1] (6)
[0041] where there are only two subfilters, one having h.sub.R, the
impulse as the response, while the other has h.sub.1, which is symmetric,
as shown in Equation (7):
h 1 = [ g 1 , g R + 1 , , g R + 1 , g 1 ]
M entries ( 7 ) ##EQU00007##
[0042] This allows for further simplification, as shown by comparing the
taps required for a subfilter performing h.sub.1 in the conventional
interpolator/decimator design, as shown in FIG. 5. As explained above,
and shown in FIG. 5, each subfilter has M taps (for each coefficient),
starting with g.sub.1 and, because of the symmetry, ending with g.sub.1.
Thus, M1 additions and M multiplications need to be performed, as shown
by the multipliers and downward arrows in FIG. 5, in the subfilter
performing h.sub.1 in the conventional interpolator/decimator design in
FIGS. 3 and 4.
[0043] However, because of the symmetry of the h.sub.1 coefficients, the
multiplications can be reduced, as shown in FIG. 6. In FIG. 6, there are
still M taps requiring M1 additions, but both taps which need to be
multiplied by the same coefficient are added together for multiplication.
To be precise, this results in .left brkttop.M/2.right brktbot..sup.1
multiplications and M1 additions, thus saving .left brktbot.M/2.right
brktbot..sup.2 multiplications. .sup.1 .left brkttop.x.right brktbot.
is the ceiling function, i.e., giving the smallest integer greater than
or equal to x..sup.2 .left brktbot.x.right brktbot. is the floor
function, i.e., giving the largest integer less than or equal to x.
[0044] The coefficients in FIGS. 5 and 6 are even symmetric (i.e.,
h.sub.1=[g.sub.1, g.sub.R+1, . . . , g.sub.R+1, g.sub.1]); however, the
architecture within a subfilter having coefficients with odd symmetry
(i.e., h.sub.1=[g.sub.1, g.sub.R+1, . . . , g.sub.R+1, g.sub.1]) can
also be simplified in the same manner, as shown in FIGS. 7 and 8.
[0045] When R=3, the underlying Nyquist filter coefficients are given in
Equation (8):
G.sub.R=3=[g.sub.1,g.sub.2,0,g.sub.4,g.sub.5,0, . . .
g.sub.3n+1,g.sub.3n+2,1,g.sub.3n+2,g.sub.3n+1, . . .
,0,g.sub.5,g.sub.4,0,g.sub.2,g.sub.1] (8)
[0046] where there are three polyphase subfilters, with functions as shown
by Equations (9)(a)9(c):
h.sub.1=[g.sub.1,g.sub.4, . . . ,g.sub.5,g.sub.2] (9)(a)
h.sub.2=[g.sub.2,g.sub.5, . . . ,g.sub.4,g.sub.1] (9)(b)
h.sub.R=3=[0,0, . . . ,1, . . . ,0,0] (9)(c)
[0047] The last subfilter, h.sub.R, as always, is the impulse response
(Eq. 9(c)), but neither h.sub.1 (Eq. 9(a)) nor h.sub.2 (Eq. 9(b)) are
symmetric (unlike Eq. 6 for R=2); however, h.sub.1 (Eq. 9(a)) and h.sub.2
(Eq. 9(b)) are antisymmetric to each other, which, as shown below,
becomes a useful property in embodiments of the present disclosure.
[0048] When R=4, the underlying Nyquist filter coefficients are given in
Equation (10):
G.sub.R=4=[g.sub.1,g.sub.2,g.sub.3,0,g.sub.5,g.sub.6,g.sub.7,0, . . .
g.sub.4n+1,g.sub.4n+2,g.sub.4n+3,1,g.sub.4n+3,g.sub.4n+2,g.sub.4n+1, . .
. ,0,g.sub.7,g.sub.6,g.sub.5,0,g.sub.3,g.sub.2,g.sub.1] (10)
[0049] where the four resulting polyphase subfilters have the functions as
shown by Equations (11)(a)11(d):
h.sub.1=[g.sub.1,g.sub.5, . . . ,g.sub.7,g.sub.3] (11)(a)
h.sub.2=[g.sub.2,g.sub.6, . . . ,g.sub.6,g.sub.2] (11)(b)
h.sub.3=[g.sub.3,g.sub.7, . . . ,g.sub.5,g.sub.1] (11)(c)
h.sub.R=4=[0,0, . . . ,1, . . . ,0,0] (11)(d)
[0050] The last subfilter, h.sub.R, as always, is the impulse response
(Eq. 11(d)), the coefficients of h.sub.2 (Eq. 11(b)) are symmetric, and
h.sub.1 (Eq. 11(a)) and h.sub.3 (Eq. 11(c)) are antisymmetric to each
other.
[0051] Generalizing the observations above to any arbitrary R for a
polyphase Nyquist filter structure: [0052] h.sub.R always has an
impulse as the impulse response; [0053] if R is even, one subfilter will
have symmetric coefficients and, if R is large enough, at least one pair
of subfilters with antisymmetric coefficients; and [0054] if R is odd,
the subfilters will all form pairs of subfilters with antisymmetric
coefficients.
[0055] Considering the prevalence of pairs of antisymmetric coefficient
subfilters, an embodiment of the present disclosure takes advantage of
their mathematical properties to further simplify the polyphase Nyquist
filter architecture, as explained below.
[0056] For an interpolator, assume function h.sub.m having antisymmetric
coefficients with function h.sub.(Rm) (which is how the antisymmetric
subfilters are themselves symmetric, e.g., h.sub.1 is antisymmetric to
h.sub.3=R1). The desired output can be written as x*h.sub.m, where x
denotes the impulse sequence and * is the convolution operator, which can
be rewritten as Equation 12(a):
x * h m = x * ( h m + h R  m 2 ) + x * ( h m
 h R  m 2 ) ( 12 ) ( a ) ##EQU00008##
[0057] Similarly, the desired output for h.sub.(Rm) can be written as
x*h.sub.(Rm), which can be further rewritten as Equation 12(b):
x * h R  m = x * ( h m + h R  m 2 )  x * (
h m  h R  m 2 ) ( 12 ) ( b ) ##EQU00009##
[0058] As can be seen in Eqs. 12(a) and 12(b), the antisymmetric pair of
h.sub.m and h.sub.(Rm) share the same terms, but differ by whether those
terms are added or one is subtracted from the other. This means the two
terms in h.sub.m and h.sub.(Rm) may only need to be calculated once,
rather than twice (in each of subfilters h.sub.m and h.sub.(Rm)), if the
appropriate architecture is used.
[0059] In other words, as shown in FIG. 9, the new pair of subfilters
replacing the two separate subfilters h.sub.m and h.sub.(Rm) would
consist of one subfilter 910 whose coefficient is
( h m + h R  m 2 ) , ##EQU00010##
and another subfilter 920 whose coefficient is
( h m  h R  m 2 ) , ##EQU00011##
and then a lattice structure which appropriately adds and subtracts those
two outputs. Thus, the output of subfilter 910 is
x * ( h m + h R  m 2 ) , ##EQU00012##
and the output of subfilter 920 is
x * ( h m  h R  m 2 ) ##EQU00013##
the two terms need to generate both x*h.sub.m (Eq. 12(a)) and
x*h.sub.(Rm) (Eq. 12(b)).
[0060] The latticework after subfilters 910 and 920 consist of feedlines
912 and 914 from subfilter 910, feedlines 922 and 924 from subfilter 920,
adder 930, and adder 940. Through this lattice, subfilter 910 output
x * ( h m + h R  m 2 ) ##EQU00014##
and subfilter 920 output
x * ( h m  h R  m 2 ) ##EQU00015##
are fed by feedlines 912 and 922, respectively, to adder 930, where they
are added together to form Eq. 12(a), as shown in FIG. 9. Similarly,
subfilter 910 output
x * ( h m + h R  m 2 ) ##EQU00016##
is fed by feedline 914 to adder 940 and subfilter 920 output
x * ( h m  h R  m 2 ) ##EQU00017##
is fed by feedline 924, in negative form, to adder 940, where they are
added together to form Eq. 12(b), as shown in FIG. 9.
[0061] This structure is generally applicable to any antisymmetric pair
h.sub.m and h.sub.(Rm).
[0062] Similarly, regarding the decimator, and assuming subfilter m having
antisymmetric coefficients with subfilter Rm, the output/summation of
all the antisymmetric pairs can be expressed as Equation (13):
m x m * h m + x R  m * h R  m = m
( x m + x R  m ) * ( h m + h R  m 2 ) + ( x
m  x R  m ) * ( h m  h R  m 2 ) ( 13 )
##EQU00018##
[0063] where x.sub.m denotes the downsampled sequence by ratio R from the
input sequence x with phase m.
[0064] Similarly to Eqs. 12(a) and 12(b), the summation on the righthand
side of Eq. 13 has antisymmetric pairs of h.sub.m and h.sub.(Rm) which
share the same terms, but differ in terms of whether those terms are
added or one is subtracted from the other. This means the two terms in
both subfilters m and (Rm) may only need to be calculated once, rather
than twice (for each subfilter), if the appropriate architecture is used.
In other words, the new pair of subfilters replacing the two separate
subfilters m and (Rm) would consist of one subfilter whose coefficient
was
( h m + h R  m 2 ) , ##EQU00019##
and another subfilter whose coefficient was
( h m  h R  m 2 ) . ##EQU00020##
[0065] However, differently than the interpolator, the lattice structure
for adding and subtracting is placed before the subfilters in the
decimator. Accordingly, the inputs to each adder in the decimator is
x.sub.m and x.sub.(Rm), with the corresponding outputs for each pair of
adders being x.sub.mx.sub.(Rm) and x.sub.m+x.sub.(Rm). The subsequent
output of each pair of subfilters is
( x m + x R  m ) * ( h m + h R  m 2 ) and
( x m  x R  m ) * ( h m  h R  m 2 ) .
##EQU00021##
[0066] FIGS. 10 and 11 are a general form of such an architecture for an
interpolator and a decimator, respectively, according to an embodiment of
the present disclosure, showing the new structure for each pair of
subfilters with antisymmetric coefficients (i.e., FIGS. 10 and 11 assume
that R is odd). A lattice structure is formed at the subfilter outputs in
the interpolator to appropriately add and subtract the outputs of the two
subfilters, and at the inputs to the subfilters in the decimator to
appropriately add and subtract the inputs of the two subfilters.
[0067] As shown in FIG. 10, interpolator 1000 has an input of N samples
which are received by a matching set of Subfilters 1 to R 1010.
Subfilters 1 and 2 and Subfilters 3 and 4 form two pairs of subfilters,
with coefficient functions in the form of
( h m + h R  m 2 ) and ( h m  h R 
m 2 ) . ##EQU00022##
Thus, in the lattice structure 1020 of interpolator 1000, each pair of
subfilters have outputs going to a pair of adders, as explained in detail
in reference to FIG. 9. The parallel outputs of each pair of adders
corresponding to a pair of subfilters constitute the antisymmetric
coefficient output, which is input to paralleltoserial converter (P2S)
1030 which outputs a serial stream of RN samples.
[0068] As shown in FIG. 11, decimator 1100 has an input of a serial stream
of RN samples which are received by a serialtoparallel converter (S2P)
1110. The S2P 1110 outputs R parallel streams of N samples into the
lattice structure 1120 of decimator 1100, in which pairs of adders
correspond to the pairs of subfilters with coefficient functions in the
form of
( h m + h R  m 2 ) and ( h m  h R  m
2 ) ##EQU00023##
among Subfilters 1 to R 1130. The parallel outputs of Subfilters 1 to R
1130 in decimator 1100 are added in 1135 to produce an output of N
samples.
[0069] Although FIGS. 10 and 11 are meant to show the general form of
architecture of an interpolator and decimator according to an embodiment
of the present invention, what is shown in FIGS. 10 and 11 also
corresponds to specific architecture when R=5. For example, when R=5,
there will be five functions, h.sub.1, h.sub.2, h.sub.3, h.sub.4, and
h.sub.5. The impulse response function is h.sub.5=R, and, because
R=5=odd, and the remaining functions are antisymmetric pairs, namely,
h.sub.1 (m=1) and h.sub.4 (Rm=4), and h.sub.2 (m=2) and h.sub.3 (Rm=3).
The resulting polyphase architecture according to embodiments of the
present disclosure looks like FIGS. 10 and 11, with two pairs of
subfilters, and impulse response subfilter R=5 at the bottom for function
h.sub.R=h.sub.5. Subfilters 1 and 2 in FIG. 10 would be for the
antisymmetric pair h.sub.1 and h.sub.4, and subfilters 3 and 4 would be
for the antisymmetric pair h.sub.2 and h.sub.3.
[0070] Based on the above, the following may be stated concerning applying
embodiments of the present disclosure to a polyphase Nyquist filter
structure with any arbitrary R: [0071] h.sub.R always has the impulse
as the impulse response; [0072] if R is even, one subfilter will have
symmetric coefficients and the remaining R2 subfilters will form
[0072] R  2 2 ##EQU00024## pairs of summers Having antisymmetric
coefficients; and [0073] if R is odd, the remaining R1 subfilters will
form
[0073] R  1 2 ##EQU00025## pairs of subfilters having
antisymmetric coefficients.
[0074] The approach according to embodiments of the present disclosure
requires less computations than the legacy approach.
[0075] In the legacy approach, where R1 subfilters have length M and R is
odd, each subfilter needs M multiplications and M1 additions. The total
number of multiplications and additions when R is odd are M(R1) and
(M1)(R1), respectively. When R is even, there is one subfilter with
symmetric coefficients, whose number of multiplications can be reduced to
.left brkttop.M/2.right brktbot. multiplications and M1 additions,
thus saving .left brktbot.M/2.right brktbot. multiplications, as
discussed above. The total number of multiplications for even R is
M(R2)+.left brkttop.M/2.right brktbot.. The number of total additions
is the same as odd R.
[0076] According to embodiments of the present disclosure, the pairing and
new structure for antisymmetric coefficient subfilters (which, in a
sense, results in symmetric coefficients) means that R1 subfilters have
symmetric coefficients whether R is odd or even. Thus, the total number
of multiplications is always .left brkttop.M/2.right brktbot.(R1).
However, the number of additions is greater: an extra R1 additions for
odd R and an extra R2 additions for even R.
[0077] Table 1 provides a summary of these differences.
TABLEUS00001
TABLE 1
Complexity Comparison for a polyphase interpolator generating R output
samples
The # of multiplications The # of additions
Legacy approach New efficient approach Saving Legacy approach New
efficient approach Cost
Odd R M(R  1) .left brkttop.M/2.right brktbot.(R  1) .left
brktbot.M/2.right brktbot. (R  1) (M  1)(R  1) M(R  1) R  1
Even R M(R  2) + .left brkttop.M/2.right brktbot. .left
brkttop.M/2.right brktbot.(R  1) .left brktbot.M/2.right brktbot. (R
 2) (M  1)(R  1) (M  1)(R  1) + (R  2) R  2
[0078] To verify these projections, a simulation was performed with legacy
architectures and architectures based on the new approach herein for R=1
through 5, and subfilter length M=2 through 10. The relative
multiplication complexity is shown in FIG. 6A, while the relative
addition complexity is shown in FIG. 6B.
[0079] In the HBF case (R=2), the legacy and new approaches have the same
number of multiplications and the new approach has more additions. In the
case of a thirdband filter (TBF) (R=3), the new approach saves 2.left
brktbot.M/2.right brktbot. multiplications at the cost of two extra
additions. The multiplications of the new approach are almost half those
of the legacy approach.
[0080] Speaking more generally, some of the distinct features of
embodiments of the present disclosure include, but are not limited to:
[0081] Restructuring pairs of antisymmetric subfilters into symmetric
subfilters; [0082] A lattice structure of adders after the subfilters in
the interpolators, and a lattice structure of adders before the
subfilters in the decimators; and [0083] The number of multiplications
are reduced by .left brktbot.M/2.right brktbot.(R.gamma.) at the cost
of R.gamma. additions (where .gamma.=1 when R is odd, and .gamma.=2 when
R is even).
[0084] A new efficient polyphase architecture for sampling rate conversion
according to embodiments of the present disclosure is described herein,
which involves generating a new set of subfilter coefficients based on
any symmetry/antisymmetry found in the conventional set of subfilter
coefficients so that any pair of conventional subfilter coefficients that
exhibit symmetry/antisymmetry are combined into a simplified new
architecture which produces the same overall output as using the
conventional set of subfilter coefficients. In one embodiment, any pair
of conventional subfilter coefficients that exhibit antisymmetry are
combined into an architecture including a pair of adders, a lattice
structure feeding the pair of adders, and a pair of subfilters whose
location depends on the implementation (e.g., before the lattice
structure in an interpolator, after the pair of adders in a decimator),
where the pair of subfilters have new coefficients based on the
antisymmetry of the conventional pair of subfilter coefficients.
[0085] The new architecture is applicable to any integer or fractional R
interpolator, decimator, or fractionalrate conversion filter. Moreover,
the new architecture can be generalized from Nyquist filters as described
herein to linearphase FIR or any type of FIR filters.
[0086] The combining of inputs or outputs to the subfilters according to
embodiments of the present disclosure can be implemented in a wide
variety of ways, as would be understood by one of ordinary skill in the
art. Thus, although the lattice structure in the polyphase interpolator
receives the output of the subfilters and the lattice structure in the
polyphase decimator generates the input of the subfilters in an
embodiment described herein, the present disclosure is not limited to
such placement.
[0087] Moreover, the present disclosure is not limited to the lattice
structures described in reference to the embodiments herein, but include
other lattice structures and implementations. For example, a simple
multiplication in the form of a bit shift may be implemented on the cross
paths of the lattice structure, as shown in FIG. 14, where the
multiplication coefficients k.sub.1 and k.sub.2 are in the form of power
of 2. As another example, the lattice structure may be connected to more
than a pair of adders and become a fully connected linear network, with 3
or more inputs and outputs, as shown in FIG. 15.
[0088] As yet another example, a lattice structure having groups of 4
subfilters could be generated by exploiting the Hadamard matrix operation
from 2 dimensions to 4 dimensions. We first explain the perspective of
Hadamard matrix operation for aforementioned example in two dimensions,
let s' denote the lefttoright flip of sequence s. The initial set of
subfilter coefficients with antisymmetric property can be shown as each
row in the matrix described in Equation (14)(a) below:
[ s 1 s 2 s 2 ' s 1 ' ] ( 14 ) ( a )
##EQU00026##
and the lattice transform can be written as leftmultiplying the above
matrix with dimension2 Hadamard matrix H.sub.2 as
[ 1 1 1  1 ] H 2 [ s 1 s 2
s 2 ' s 1 ' ] = [ s 1 + s 2 ' s 2 + s 1 '
s 1  s 2 ' s 2  s 1 ' ] = [ s 1 + s 2 '
( s 1 + s 2 ' ) ' s 1  s 2 '  ( s 1  s 2
' ) ' ] ( 14 ) ( b ) ##EQU00027##
[0089] where the righthand side indicates the pair of two symmetric
subfilters according to the present disclosure, which cuts down the
number of multipliers by 1/2 for each subfilter.
[0090] To generalize to 4 subfilters, the original 4 subfilter
coefficients would fit the description as indicated by Equation (15)(a).
And the righthand side of Equation (15)(b) indicates a group of four
symmetric subfilters according to the present disclosure, which cuts down
the number of multipliers by 1/4 for each subfilter:
[ s 1 s 3 s 4 s 2 s 2 ' s 4 ' s 3
' s 1 ' s 3 s 1 s 2 s 4 s 4 ' s 2 ' s
1 ' s 3 ' ] ( 15 ) ( a ) [ 1 1 1 1
1  1 1  1 1 1  1  1 1  1  1
1 ] H 4 [ s 1 s 3 s 4 s 2 s 2 '
s 4 ' s 3 ' s 1 ' s 3 s 1 s 2 s 4 s 4 '
s 2 ' s 1 ' s 3 ' ] = [ s 1 + s 2
' + s 3 + s 4 ' s 3 + s 4 ' + s 1 + s 2 ' s 4 + s
3 ' + s 2 + s 1 ' s 2 + s 1 ' + s 4 + s 3 ' s 1
 s 2 ' + s 3  s 4 ' s 3  s 4 ' + s 1  s 2 ' s
4  s 3 ' + s 2  s 1 ' s 2  s 1 ' + s 4  s 3 '
s 1 + s 2 '  s 3  s 4 ' s 3 + s 4 '  s 1  s 2 '
s 4 + s 3 '  s 2  s 1 ' s 2 + s 1 '  s 4  s 3 '
s 1  s 2 '  s 3 + s 4 ' s 3  s 4 '  s 1 + s
2 ' s 4  s 3 '  s 2 + s 1 ' s 2  s 1 '  s 4 +
s 3 ' ] = [ s 1 + s 2 ' + s 3 + s 4 ' s
1 + s 2 ' + s 3 + s 4 ' ( s 1 + s 2 ' + s 3 + s 4 '
) ' ( s 1 + s 2 ' + s 3 + s 4 ' ) ' s 1  s 2 '
+ s 3  s 4 ' s 1  s 2 ' + s 3  s 4 '  ( s 1
 s 2 ' + s 3  s 4 ' ) '  ( s 1  s 2 ' + s 3 
s 4 ' ) ' s 1 + s 2 '  s 3  s 4 '  ( s 1 +
s 2 '  s 3  s 4 ' )  ( s 1 + s 2 '  s 3  s 4 '
) ' ( s 1 + s 2 '  s 3  s 4 ' ) ' s 1  s 2
'  s 3 + s 4 '  ( s 1  s 2 '  s 3 + s 4 ' )
( s 1  s 2 '  s 3 + s 4 ' ) '  ( s 1  s 2 ' 
s 3 + s 4 ' ) ' ] ( 15 ) ( b ) ##EQU00028##
[0091] The steps and/or operations described above in relation to an
embodiment of the present disclosure may occur in a different order, or
in parallel, or concurrently for different epochs, etc., depending on the
specific embodiment and/or implementation, as would be understood by one
of ordinary skill in the art. Different embodiments may perform actions
in a different order or by different ways or means. As would be
understood by one of ordinary skill in the art, some drawings are
simplified representations of the actions performed, their descriptions
herein simplified overviews, and realworld implementations would be much
more complex, require more stages and/or components, and would also vary
depending on the requirements of the particular implementation. Being
simplified representations, these drawings do not show other required
steps as these are known and understood by one of ordinary skill in the
art and may not be pertinent and/or helpful to the present description.
[0092] Similarly, some drawings are simplified block diagrams showing only
pertinent components, and some of these components merely represent a
function and/or operation wellknown in the field, rather than an actual
piece of hardware, as would be understood by one of ordinary skill in the
art. In such cases, some or all of the components/modules may be
implemented or provided in a variety and/or combinations of manners, such
as at least partially in firmware and/or hardware, including, but not
limited to one or more applicationspecific integrated circuits
("ASICs"), standard integrated circuits, controllers executing
appropriate instructions, and including microcontrollers and/or embedded
controllers, fieldprogrammable gate arrays ("FPGAs"), complex
programmable logic devices ("CPLDs"), and the like. Some or all of the
system components and/or data structures may also be stored as contents
(e.g., as executable or other machinereadable software instructions or
structured data) on a nontransitory computerreadable medium (e.g., as a
hard disk; a memory; a computer network or cellular wireless network or
other data transmission medium; or a portable media article to be read by
an appropriate drive or via an appropriate connection, such as a DVD or
flash memory device) so as to enable or configure the computerreadable
medium and/or one or more associated computing systems or devices to
execute or otherwise use or provide the contents to perform at least some
of the described techniques.
[0093] One or more processors, simple microcontrollers, controllers, and
the like, whether alone or in a multiprocessing arrangement, may be
employed to execute sequences of instructions stored on nontransitory
computerreadable media to implement embodiments of the present
disclosure. In some embodiments, hardwired circuitry may be used in
place of or in combination with software instructions. Thus, embodiments
of the present disclosure are not limited to any specific combination of
hardware circuitry, firmware, and/or software.
[0094] The term "computerreadable medium" as used herein refers to any
medium that stores instructions which may be provided to a processor for
execution. Such a medium may take many forms, including but not limited
to, nonvolatile and volatile media. Common forms of nontransitory
computerreadable media include, for example, a floppy disk, a flexible
disk, hard disk, magnetic tape, or any other magnetic medium, a CDROM,
any other optical medium, punch cards, paper tape, any other physical
medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASHEPROM,
any other memory chip or cartridge, or any other medium on which
instructions which can be executed by a processor are stored.
[0095] Some embodiments of the present disclosure may be implemented, at
least in part, on a portable device. "Portable device" and/or "mobile
device" as used herein refers to any portable or movable electronic
device having the capability of receiving wireless signals, including,
but not limited to, multimedia players, communication devices, computing
devices, navigating devices, etc. Thus, mobile devices include (but are
not limited to) user equipment (UE), laptops, tablet computers, Portable
Digital Assistants (PDAs), mp3 players, handheld PCs, Instant Messaging
Devices (IMD), cellular telephones, Global Navigational Satellite System
(GNSS) receivers, watches, or any such device which can be worn and/or
carried on one's person.
[0096] Various embodiments of the present disclosure may be implemented in
an integrated circuit (IC), also called a microchip, silicon chip,
computer chip, or just "a chip," as would be understood by one of
ordinary skill in the art, in view of the present disclosure. Such an IC
may be, for example, a broadband and/or baseband modem chip.
[0097] While several embodiments have been described, it will be
understood that various modifications can be made without departing from
the scope of the present disclosure. Thus, it will be apparent to those
of ordinary skill in the art that the present disclosure is not limited
to any of the embodiments described herein, but rather has a coverage
defined only by the appended claims and their equivalents.
* * * * *