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United States Patent 3,622,762
Dyer ,   et al. November 23, 1971

CIRCUIT DESIGN BY AN AUTOMATED DATA PROCESSING MACHINE

Abstract

Using representations of circuit topologies and initial values of all elements, a circuit design may be modified by an automated data processing machine to improve operation for at least one performance characteristic by changing design variables. A desired circuit topology is selected and the initial values for all the circuit elements are coded and stored in the data processor. In addition, the desired performance characteristic is also selected and coded. Using coded input information, the data processor generates and stores a representation of a continuous analytical objective function. In the operation of the data processor, a value of the objective function is generated and stored. This value is dependent upon the sum of a power function of the difference between an actual performance and a specified performance characteristic. To obtain a specified performance characteristic for a given circuit topology, the value of the objective function is improved.


Inventors: Dyer; Lester W. (Plano, TX), Houston; Theodore W. (Richardson, TX), Policky; Gary J. (Plano, TX)
Assignee: Texas Instruments Incorporated (Dallas, TX)
Appl. No.: 04/833,892
Filed: June 11, 1969


Current U.S. Class: 716/102 ; 716/106; 716/135; 968/579
Current International Class: G04C 19/00 (20060101); G06F 17/50 (20060101); G04C 19/04 (20060101); G06f 015/56 ()
Field of Search: 235/150


Other References

"Computer-Aided Design of Microwave Integrated Circuits;" IEEE-Wescon Tech Papers; Vol. 13 pt. 2; Session 6/6/69; pp. 1-3; Houston, Dyer, & Policky .
"Optimal Design of Matching Networks for Microwave Transistor Amplifiers;" IEEE Transactions on Microwave Theory and Techniques; Vol. MTT-14; pp. 696-698; Dec. 1966; F. E. Emery and M. O'Hagan .
"Design of Digital Loaded-Line Phase-Shift Networks for Microwave Thin-Film Applications;" IEEE Transactions on Microwave Theory and Techniques; Vol. MTT-16, No. 7; July 1968; Frances L. Opp and W. F. Hoffman.

Primary Examiner: Morrison; Malcolm A.
Assistant Examiner: Wise; Edward J.

Claims



Having described the invention in accordance with applicable United States statutes, we claim:

1. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial element values,

b. generating and storing a value of said continuous objective function which depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits, and

c. modifying at least one of the design variables in a direction and by an amount dependent on said objective function to improve the generated and stored value thereof.

2. The method of designing a circuit by an automated data processing machine as set forth in claim 1 wherein the generated and stored value of said continuous objective function depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits and a greater than, less than or equal to difference between the specified performance characteristic and the synthesized performance characteristic.

3. The method of designing a circuit by an automated data processing machine as set forth in claim 1 including repeating steps (a), (b) and (c) for a preselected number of passes utilizing the design variables as modified in the previous pass to generate and store a new objective function and to further improve the generated and stored value of the new objective function.

4. The method of designing a circuit by an automated data processing machine as set forth in claim 3 including the step of analyzing the selected circuit topology at the final values of the circuit elements.

5. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial element values,

b. generating and storing a value of said continuous objective function which depends on the sum, over a range of frequencies, of a power function wherein a synthesized performance characteristic may be less than, greater than, or equal to a specified performance characteristic, and

c. modifying at least one of the design variables in a direction and by an amount dependent on said objective function to improve the generated and stored value thereof.

6. The method of designing a circuit by an automated data processing machine as set forth in claim 5 including repeating steps (a), (b) and (c) for a preselected number of passes utilizing the design variables as modified in the previous pass to generate and store a new objective function and to further improve the generated and stored value of the new objective function.

7. The method of designing a circuit by an automated data processing machine as set forth in claim 6 including the step of analyzing the selected circuit topology at the final values of the circuit elements.

8. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial element values,

b. generating and storing representations of analytical derivatives of said objective function with respect to design variables,

c. generating and storing a value of said continuous objective function which depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits, and

d. modifying at least one of the design variables in a direction and by an amount dependent on said objective function and said representations of the analytical derivatives to improve the generated and stored value of the objective function.

9. The method of designing a circuit by an automated data processing machine as set forth in claim 8 wherein the generated and stored value of said continuous objective function depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits and a greater than, less than or equal to difference between the specified performance characteristic and the synthesized performance characteristic.

10. The method of designing a circuit by an automated data processing machine as set forth in claim 9 including repeating steps (a), (b), (c) and (d) for a preselected number of passes utilizing the design variables as modified in the previous pass to generate and store a new objective function and to further improve the generated and stored value of the objective function.

11. The method of designing a circuit by an automated data processing machine as set forth in claim 9 wherein the continuous objective function is modified by ignoring the differences between said specified performance characteristic and said synthesized performance characteristic within a selected tolerance band at selected frequencies over said range of frequencies.

12. The method of designing a circuit by an automated data processing machine as set forth in claim 9 wherein the continuous analytical objective function is modified by ignoring negative differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

13. The method of designing a circuit by an automated data processing machine as set forth in claim 9 wherein the continuous analytical objective function is modified by ignoring positive differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

14. The method of designing a circuit by an automated data processing machine as set forth in claim 9 wherein the continuous analytical objective function is modified by ignoring 0 differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

15. The method of designing a circuit by an automated data processing machine as set forth in claim 8 wherein the continuous analytical objective function comprises at least one of the options selected from the following options:

a. f.sub.k -(GN(f.sub.k)-GREF(f.sub.k)).sup.2

wherein the calculated gain GN at sampled frequencies f.sub.k is least-squared-error fit to the a reference gain GREF:

b. f.sub.k -(GN(f.sub.k)-GFLOAT).sup.2

wherein the calculated gain GN at sampled frequencies f.sub.k is least-squared-error fit to a floating flat reference gain GFLOAT;

c. f.sub.k (GFLOAT-GFLOATMAX)

wherein GFLOATMAX is the maximum limit of the amplitude of a floating reference gain GFLOAT and GFLOAT is maximized at sampled frequencies f.sub.k ;

d. f.sub.k -(NF(f.sub.k)-SPECNF).sup.2

wherein the calculated noise figure NF at sampled frequencies f.sub.k is least-squared-error fit to a reference noise figure SPECNF;

e. f.sub.k -(MMS(f.sub.k)).sup.2

wherein the calculated source mismatch MMS at sampled frequencies f.sub.k is least-squared-error fit to zero source mismatch;

f. f.sub.k -(MML(f.sub.k)).sup.2

wherein the calculated load mismatch MML at sampled frequencies f.sub.k is least-squared-error fit to zero load mismatch;

g. f.sub.k .DELTA.fe-(GN(f.sub.k +.DELTA.fe)-GREF(.DELTA.fe)).sup.2

wherein the calculated gain GN at sampled frequencies f.sub.k +.DELTA.fe, where f.sub.k are center frequencies and .DELTA.fe define a distribution of sampling about such center frequencies, is least-squared-error fit to a reference gain GREF;

h. f.sub.k -((real(Z(IIN,IIN)-ZSPEC11)).sup.2

+(imaginary(Z(IIN,IIN)-ZSPEC11)).sup.2 +...

+(imaginary(Z(IOUT,IOUT)-ZSPEC22)).sup.2)

wherein the impedance matrix Z of the circuit at sampled frequencies f.sub.k is least-squared-error fit to an impedance matrix

ZSPEC11 ZSPEC12

ZSPEC21 ZSPEC22

where IIN is the node number assigned to the input node and IOUT is the node number assigned to the output node; and

i. f.sub.k -(PH(f.sub.k)-PHREF(f.sub.k)-PFLOAT-SFLOAT*f.sub.k).sup.2

wherein the calculated phase PH at sampled frequencies f.sub.k is least-squared-error fit to a reference phase PHREF and where PFLOAT and SFLOAT are optimization parameters.

16. The method of designing a circuit by an automated data processing machine as set forth in claim 8 wherein the continuous analytical objective function is modified by ignoring negative differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

17. The method of designing a circuit by an automated data processing machine as set forth in claim 8 wherein the continuous analytical objective function is modified by ignoring positive differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

18. The method of designing a circuit by an automated data processing machine as set forth in claim 8 wherein the continuous analytical objective function is modified by ignoring 0 differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

19. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial element values,

b. generating and storing representations of analytical derivatives of said objective function,

c. generating and storing a value of said continuous objective function which depends on the sum, over a range of frequencies, of a power function wherein a synthesized performance characteristic may be less than, greater than, or equal to a specified performance characteristic, and

d. modifying at least one of the design variables in a direction and by an amount dependent on said objective function and said representations of the analytical derivatives to improve the generated and stored value of the objective function.

20. The method of designing a circuit by an automated data processing machine as set forth in claim 19 including repeating steps (a), (b), (c) and (d) for a preselected number of passes utilizing the design variables as modified in the previous pass to generate and store a new objective function and to further improve the generated and stored value of the objective function.

21. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing representations of an admittance matrix of the selected circuit topology and initial element values,

b. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial element values with said admittance matrix,

c. generating and storing a value of said continuous objective function which depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits, and

d. modifying at least one of the design variables in a direction by an amount dependent on said objective function to improve the generated and stored value thereof.

22. The method of circuit design by an automated data processing machine as set forth in claim 21 including:

e. generating and storing representations of analytical derivatives with respect to the design variables of said objective function and wherein the design variables are modified in part by an amount dependent on said analytical derivatives and said objective function.

23. The method of circuit design by an automated data processing machine as set forth in claim 22 including repeating steps (a), (b), (c), (d) and (e) for a preselected number of passes using values of the design variables as modified in the previous pass to generate and store a new objective function and to further improve the generated and stored value of the new objective function.

24. The method of designing a circuit by an automated data processing machine as set forth in claim 23 wherein the generated and stored value of said continuous objective function depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits and a greater than, less than, or equal to difference between the specified performance characteristic and the synthesized performance characteristic.

25. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial values at one of the operating modes,

b. generating and storing a value of said continuous objective function which depends upon the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic for the selected mode and a synthesized performance characteristic for that mode beyond preset limits,

c. repeating steps (a) and (b) for the remainder of the operating modes to generate a continuous analytical objective function and the value thereof for each mode,

d. generating and storing a composite objective function by a summation of all the individual mode objective functions, and

e. modifying at least one of the design variables in a direction and by an amount dependent on the composite objective function to improve the generated and stored value thereof.

26. The method of designing a circuit by an automated data processing machine as set forth in claim 25 wherein the generated and stored value of said continuous objective function depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits and a greater than, less than, or equal to difference between the specified performance characteristic and the synthesized performance characteristic.

27. The method of designing a circuit by an automated data processing machine as set forth in claim 26 including repeating steps (a), (b), (c), (d) and (e) for a selected number of passes for each operating mode utilizing design variables of a previous pass to generate and store a new objective function for each mode and a new composite objective function to further improve the generated and stored value of the objective function.

28. The method of designing a circuit by an automated data processing machine as set forth in claim 27 including the step of analyzing the selected circuit topology at the final values of the circuit elements for each operating mode.

29. The method of designing a circuit by an automated data processing machine as set forth in claim 27 wherein the continuous analytical objective function comprises at least one of the options selected from the following options:

a. f.sub.k -(GN(f.sub.k)-GREF(f.sub.k)).sup.2

wherein the calculated gain GN at sampled frequencies f.sub.k is least-squared-error fit to a reference gain GREF;

b. f.sub.k -(GN(f.sub.k)-GFLOAT).sup.2

wherein the calculated gain GN at sampled frequencies f.sub.k is least-squared-error fit to a floating flat reference gain GFLOAT;

c. f.sub.k (GFLOAT-GFLOATMAX)

wherein GFLOATMAX is the maximum limit of the amplitude of a floating reference gain GFLOAT and GFLOAT is maximized at sampled frequencies f.sub.k ;

d. f.sub.k -(NF(f.sub.k)-SPECNF).sup.2

wherein the calculated noise figure NF at sampled frequencies f.sub.k is least-squared-error fit to a reference noise figure SPECNF;

e. f.sub.k -(MMS(f.sub.k)).sup.2

wherein the calculated source mismatch MMS at sampled frequencies f.sub.k is least-squared-error fit to zero source mismatch;

f. f.sub.k -(MML(f.sub.k)).sup.2

wherein the calculated load mismatch MML at sampled frequencies f.sub.k is least-squared-error fit to zero load mismatch;

g. f.sub.k .DELTA.fe-(GN(f.sub.k +.DELTA.fe)-GREF(.DELTA.fe)).sup.2

wherein the calculated gain GN at sampled frequencies f.sub.k +.DELTA.fe, where f.sub.k are center frequencies and .DELTA.fe define a distribution of sampling about such center frequencies, is least-squared-error fit to a reference gain GREF;

h. f.sub.k -((real(Z(IIN,IIN)-ZSPEC11)).sup.2

+(imaginary (Z(IIN,IIN)-ZSPEC11)).sup.2 +...

+(imaginary (Z(IOUT,IOUT)-ZSPEC22)).sup.2)

wherein the impedance matrix Z of the circuit at sampled frequencies f.sub.k is least-squared-error fit to an impedance matrix

ZSPEC11 ZSPEC12

ZSPEC21 ZSPEC22

where IIN is the node number assigned to the input node and IOUT is the node number assigned to the output node; and

i. f.sub.k -(PH(f.sub.k)-PHREF(f.sub.k)-PFLOAT-SFLOAT*f.sub.k).sup.2

wherein the calculated phase PH at sampled frequencies f.sub.k is least-squared-error fit to a reference phase PHREF and where PFLOAT and SFLOAT are optimization parameters.

30. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing representations of an admittance matrix of the selected circuit topology and initial element values for one of the operating modes,

b. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial element values with said admittance matrix for the selected operating mode,

c. generating and storing a value of said continuous objective function which depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic for the selected mode and a synthesized performance characteristic for that mode beyond preset limits,

d. repeating steps (a), (b) and (c) for the remainder of the operating modes to generate a continuous analytical objective function and the value thereof for each operating mode,

e. generating and storing a composite objective function by a summation of all the individual mode objective functions,

f. modifying at least one of the design variables in a direction by an amount dependent on the composite objective function to improve the generated and stored value thereof.

31. The method of designing a circuit by an automated data processing machine as set forth in claim 30 including:

g. generating and storing representations of analytical derivatives with respect to the design variables of said objective function and wherein the design variables are modified in part by an amount dependent on said analytical derivatives and said objective function.
Description



This invention relates to circuit design, and more particularly to optimization of a circuit design by means of an automated data processing machine.

Circuit designing for years has been the task of an engineer calculating various circuit parameters with a slide rule and paper and pencil. Typically, an engineer is assigned the task of designing a circuit having certain performance characteristics. Either from memory or from a reference text, he selects a circuit topology having known performance characteristics similar to those desired. The designer then calculates the value of each circuit element for a specific performance characteristic. The end result is a circuit that is intended to operate in accordance with the assigned performance characteristic. The final circuit, however, is usually a compromise from what is desired.

In recent years, considerable emphasis has been placed on computerized designs in all fields including electronic circuits, and, as expected, in many cases the computer has outperformed the engineer. It must be recognized, however, that a computer is only a tool in the hands of the design engineer replacing his slide rule. Thus, a computer-designed circuit may be no better than that produced by an engineer using a slide rule. For example, a wide band linear amplifier consisting of several stages might be designed by considering each circuit element of each stage individually and then cascading the results to obtain the desired overall effect. This, in essence, is the same procedure used by the engineer in his manual computations. The desired band width might be achieved by either stagger-tuning or single-tuning the stages. Whether the end result is an amplifier having stagger-tuning or single-tuning depends on the instructions to the computer. In effect, the computer merely relieves the engineer of his slide rule calculations. The final circuit design may operate no better than that designed by hand calculations.

In accordance with the present invention, an engineer selects a representative circuit topology and assigns initial values to all the circuit elements. This information is coded into a computer along with selected options that outline a specified circuit performance characteristic. The automated data processing machine, using a program listing, then considers the overall circuit topology in light of the desired performance characteristic and provides an optimized circuit design. Using the program listing, the data processor changes design variables, including circuit elements, in a manner that is not limited to any specific design approach. The process considers the entire circuit as a whole, and not individual parts that must later be combined. Consider the previous example, all the design variables of the several stages are evaluated simultaneously to improve the performance as specified by selected performance characteristics. The final circuit design may be stagger-tuned, singled-tuned, or some combination. A data processor operating in accordance with the present invention is not limited to any specified approach. Rather, it is free to choose the approach that provides optimized circuit operation.

In designing a circuit, the automated data processor constructs an admittance matrix and the first derivative thereof with respect to the design variables. The admittance matrix and the first derivative are then used to generate a continuous analytical objective function in accordance with the performance characteristic options selected by the user. The first derivative of the objective function is also generated by the processor. Both the objective function and its first derivative are called by an optimizer routine that modifies at least one of the design variables in a direction and by an amount dependent on the objective function and the objective function derivative. Using the modified design values, a selected circuit topology is then reconsidered to determine if additional improvement is possible. An optimized circuit design is achieved by considering the selected circuit topology and the objective function over a range of frequencies.

To optimize a particular circuit topology to achieve a given performance characteristic, the objective function includes terms for the sum of a power function of the difference between a specified performance characteristic and a calculated performance over a range of frequencies. Where applicable, the objective function includes a term to minimize the difference between an actual performance characteristic and a specified performance characteristic beyond preset limits. Further, the objective function may include terms such that the final circuit design will operate at a given frequency either at, below, or above a specified value of a performance characteristic.

Further, in accordance with the process of the present invention, an automatic data processing machine will optimize the operation of a circuit that includes elements that may be switched into and out of the circuit, that is, a circuit that has several operating modes. Again, the data processor considers the entire circuit as a whole. An admittance matrix and the first derivative thereof with respect to the design variables is constructed for each of the several operating modes. A composite objective function is then generated using the admittance matrix and the first derivative for each of the several operating modes. The composite objective function is then called by the optimizer routine that modifies design variables throughout the several operating modes in a direction and by an amount dependent on the composite objective function and the objective function derivative. As explained, the design values modified in the optimizer routine are then used to determine if additional improvement is possible.

The improvements in circuit operation achieved by the method of the present invention is primarily the result of generating a continuous analytical objective function that has a continuous first derivative. This continuous analytical objective function and its continuous first derivative are generated in a routine that employs the admittance matrix of a selected circuit topology and the first derivative of the matrix. Both the objective function and the first derivative are inputs to an optimizer routine. In the optimizer routine the original element values are adjusted in a manner to improve a numerical representation of the objective function. The optimizer routine may be repeated several times, each time using a new value of the objective function and its first derivative (generated from design variables modified in the previous optimizer pass) to further adjust the circuit element values. This readjustment continues for a preselected number of passes at a preselected number of frequency points to produce the best possible circuit design.

A more complete understanding of the invention and its advantages will be apparent from the specification and claims, and from the accompanying drawings illustrative of the invention.

Referring to the drawings:

FIG. 1 is a block diagram of a total automated data processing machine for generating circuit masks representing an optimized circuit design;

FIG. 2 is a basic flow chart of the optimization operation in a circuit design sequence;

FIG. 3 is a logic flow chart illustrating the method of optimizing and analyzing a circuit design;

FIG. 4 is a schematic of a single-mode representative circuit topology that may be optimized by the method of the present invention; and

FIG. 5 is a schematic of a multimode circuit which also may be optimized by the method of the present invention.

Referring to FIG. 1, there is shown a block diagram of a system for computerized design of linear time invariant electronic circuits consisting of resistors, capacitors, inductors, transmission lines, controlled current and voltage sources, circulators, transformers, and three terminal devices characterized by s or y parameters as a function of frequency and one other variable. The input to the system is a circuit topology and circuit performance criteria. Outputs include optimized values for the parameters of the circuit topology along with performance characteristics of the optimized circuit, and for microstrip circuitry a photomask for producing an optimized circuit.

Coded data of a selected circuit topology may be inputted to an analysis and optimization routine 10 from a memory storage 12 or punched cards 14. Catalog circuits in the memory storage 12 may be retrieved by an identifying code number. These circuits have been optimized for particular objectives, and can be reoptimized for different objectives or with different active device characterization data. Also, it is possible to modify the topology of the cataloged circuits by adding, changing, or deleting elements. Use of the catalog of circuits simplifies setting up the analysis and optimization routine. Where the desired circuit topology is not one of the cataloged circuits, however, the desired circuit may be coded onto the punched cards 14 as an input to the analysis and optimization routine 10.

In addition to a circuit topology and initial circuit element values, the analysis and optimization routine 10 may receive input information on active circuit components in the form of s or y parameters as a function of frequency and some second variable. Again, the device data may be inputted to the analysis and optimization routine 10 from a device memory storage 16 or device punched cards 18. In addition to device data and circuit topology and parameters, the analysis and optimization routine 10 must receive input data in the form of a design goal for the selected circuit. This design goal is an expression (objective function) which is in some way proportional to the "goodness" of the circuit. The objective function may be selected from a number of available options or prepared to satisfy a particular design goal. In either case, the objective function is inputed into the analysis and optimization routine 10 by means of punched cards 20.

After receiving input information on a desired circuit topology and initial values of all circuit elements, and at least one desired performance characteristic, the analysis and optimization routine 10 produces an output giving optimized values for the circuit elements and a circuit analysis, when requested, which is an input to a microstrip layout routine 22. For microstrip circuits, the values for the circuit elements in the output from the analysis and optimization routine 10 will include the physical length and width of the transmission lines. As an alternative, the output from the optimization routine 10 may be readout and printed on a layout parameter list 24. The information on the list 24 may then be used to punch layout data cards 26. Layout data cards may then be used at some later time to provide coded information to the microstrip layout routine 22. There usually will be one data card 26 per circuit element giving the line length and width, the nodal connection, and approximate coordinates of the end points. In addition to the optimization routine 10 and the layout cards 26, the microstrip layout routine 22 may also receive layout data from a memory drum 28. The memory drum 28 and/or the data cards 26 supplies data on the approximate configuration of the microstrip lines.

The output of the layout routine 22 consists of coordinates of the end points and bend points of all elements of the circuit topology optimized by the analysis and optimization 10. A mask 30 will be generated outlining the desired circuit topology with the optimized circuit values. This mask will be generated by means of a plotter 32, for example, a Gerber plotter, connected to the output of the layout routine 22. The layout 22 will also produce a listing of data cards 34 which may be punched for future mask generation.

Referring to FIG. 2, there is shown a basic block diagram of a logic flow chart for the optimization routine 10 for a circuit design. The program for optimization of a circuit design includes subroutines that perform nodal analysis on a specified circuit topology coupled with a subroutine of conjugate gradient optimization. After the selected circuit topology, with nodal points identified, and all circuit element values, has been coded and stored, an objective function is generated from the selected objective function options (block 36). In addition to an objective function, the first derivative or gradient thereof with respect to design variables is generated and stored. Optimization of a circuit design begins by questioning whether the selected circuit is to be optimized or channeled to an output circuit 38. If the inquiry, identified by the diamond 40, produces an answer that the selected circuit requires further optimization, then the objective function and its gradient are called by an optimizer subroutine to optimize the objective function by adjusting circuit design variables, indicated by the block 42. The selected circuit topology with the adjusted design variables is then analyzed and a new objective function and a first derivative are generated by the subroutine of block 36. The analysis compares a synthesized performance characteristic with a desired performance characteristic, as represented by the objective function.

If the desired performance characteristic has not been achieved in the last optimization and adjusting pass, a new objective function and its gradient are generated and stored based on the adjusted values of the circuit elements. Again, an inquiry is made as to whether another optimization pass will be made. If additional optimization of the circuit is desired, another pass will be made through the optimizer subroutine 42. Another adjustment of the circuit elements takes place, and another evaluation of the objective function and its gradient is made. This cycle continues until either the desired performance characteristics have been obtained, or the number of passes reaches a preset number. In either case, the selected circuit topology and final circuit element values are coupled to the output circuit 38.

Referring to FIG. 3, there is shown a logic flow chart for the optimization routine 10 including the generation of objective functions and a circuit admittance matrix. To run the optimization routine, a selected circuit topology together with initial circuit element values must be coded and made available. The suggested procedure for coding a selected topology is to sketch the circuit and label all the nodes and place identifiers on all the elements. It is not necessary that the node numbers be in any special sequence. The input and output nodes may be specified; however, if no value is specified for the input node the lowest numbered node will assume to be the input. If no value is specified for the output node, the highest numbered node is assumed to be the output. The datum node (a reference mode) is normally assumed to be the zero node. The source admittance is always connected between the input node and the reference node and the load admittance is always connected between the output node and the reference node. Source and load admittances and black box (s) or (y) parameters are inputted to the optimizer routine as a sequence of measured data points. In order to interpolate between the data points, a polynominal of specified degree is fit through these points such that the mean-squared error is minimized. Referring to the following equation:

A0+A1*F+A2*F**2+. . . +AN*F**N=Y(F) (1)

the coefficients A0, A1, ..., AN, are determined by means of the measured data points and coded and stored in the memory 46 along with the circuit topology and circuit element values. For any frequency F, the admittance Y(F) for the source, load or black box may be calculated using the above equation. As an alternative, the exact data for the source and/or load admittance at each frequency to be used in the optimization routine may be supplied and coded for storage in the memory 46. The optimization routine will then use the exact values of the source and/or load admittance. For a black box, it is possible to specify the s or y parameters as a function of some second variable, such as collector current in the case of a transistor, in addition to the frequency.

In addition to a selected circuit topology and device characterization, the optimization routine must also be supplied with at least one selection from a plurality of objective function options. The objective function may be written as follows:

OBJECTIVE FUNCTION = .SIGMA..sub.f (W.sub.1.sup.. g.sub.1 (Gain)+W.sub.2.sup.. g.sub.2 (Noise Figure)+ etc.) (2)

Where the constants W are weighting factors which allow emphasis to be placed on one or the other of the quantities to be optimized, and the g terms are arbitrary functions of the quantity in parenthesis. The term f.sub.k indicates that the objective function is formed by summing the expression at (2) over several frequencies in the range of interest. Various expressions available for use in generating an objective function are listed in table I below. ##SPC1##

When an engineer is designing an electrical circuit, he has a set of well-defined circuit characteristics and specifications which he desires the completed circuit to achieve. As previously mentioned, the design engineer selects options that outline such specified circuit performance characteristics. For example, his goal might be to maximize the gain over the frequency band for his circuit, subject to the condition that the variation in the gain over that frequency band be small. The design engineer would then examine the list of available optimization options in table I to determine if an option is included which corresponds to his design goals. In this case, he would find that a combination of options 2 and 3 correspond to these exemplary design goals. When more than one option is chosen by the design engineer, as here, he must also assign a weighing factor to each option which signifies the relative importance of one chosen option with respect to another chosen option. That is, the design engineer might determine that the goals of the circuit which he is designing require optimization according to options 4 and 5 of table I. By optimizing according to option 4, however, the characteristics according to option might become less optimized; while, by optimizing 5, 4 might become less optimized, these being unavoidable characteristics of the physical laws of electricity. The design engineer must then assign relative weights to each of the objective function selected. Thus, where the design engineer's circuit requirements as to the relative importance of options 4 and 5 are equal, an equal weight would be assigned to each. On the other hand, if the design engineer's circuit requirements are such that, although optimization according to options 4 and 5 are desired, the optimization according to the equation of option 5 is more important that that of option 4, a higher weighing factor will be given to option 5. The relative importance given to each by the processing machine is determined by the actual weighing factor assigned to each which is totally in the control of the design engineer to exactly meet his circuit goals. This same procedure is used for any other set of design specifications which the engineer might have for a circuit he is designing. A more detailed explanation of the optimization of characteristics for a specific circuit is later described in detail with respect to FIG. 4.

In addition to the objective function options, the memory 46 must also receive coded data on the number of frequency points at which the circuit topology will be evaluated to meet the selected performance characteristic. Further, the memory 46 must receive instructions as to the maximum number of passes through the optimizer routine for evaluating the selected circuit.

With all the above instructions coded into the system, the optimization routine first inquires as to whether or not optimization of the selected topology is desired. If optimization of the selected circuit topology is to be bypassed, the number of passes through the optimizer will be zero (N=0)as indicated by the block 48. In this case, the selected circuit topology data and the values of the circuit elements will bypass the optimization routine, and instead be transferred to a circuit analysis routine to be described.

If N (the number of optimizer passes) is greater than zero, however, then the selected circuit topology will be optimized. To optimize and adjust a selected circuit, the routine generates an admittance matrix (Y-matrix) from the selected circuit topology as identified by the block 50. By using nodal analysis, a full n.times.n admittance matrix for the selective circuit may be formed in most cases. To reduce the order of an admittance matrix, series or cascaded elements are reduced to a single 2.times.2 matrix which is then added to the system Y-matrix. This procedure is known as ABCD reduction. To generate the admittance or Y-matrix, the system goes through the selected circuit, element by element, cumulatively adding the contributions of each element to the matrix. In many cases the admittance matrix for a circuit will be sparse, i.e., many of the entries are zero.

In addition to the admittance matrix, the first derivative of the matrix is formed by the routine of block 50. Further, as indicated by the block 52, the system has a special matrix inverting routine which takes advantage of the sparsity of the Y-matrix to produce an inverted Y-matrix or Z-matrix which can be used to readily obtain most characteristics of a selected circuit.

Assuming that at least one performance characteristic has been selected such that J (the number of chosen objective function options) is not zero, then the routine of block 54 will generate and store an objective function and the first derivative thereof with respect to the design variables. From the objective function and its first derivative, a numerical value thereof will be generated and stored for circuit optimization. The objective function is generated from the options selected from table I. Using the value of the objective function and the value of the objective function gradient, an optimizer subroutine of block 56 adjusts circuit design variables in a manner dependent upon the objective function and its gradient.

The optimizer subroutine (block 56) may be thought of as trying to find the highest point in an m-dimensional space, where m is the number of variables, and the height is the value of the objective function. By placing constraints on the variables, i.e., the circuit elements, boundaries are formed in this m-dimensional space. The optimizer routine of block 56 uses the conjugate gradient of the objective function and the value of the gradient of the objective function in finding the "highest" point, that is, a circuit that operates as near as possible to the selected performance characteristics.

First the objective function and its gradient are evaluated at some feasible starting point in the m-dimensional space. Having initially evaluated the objective function gradient, the next step is to optimize by adjusting a circuit element to produce a value for the objective function in the steepest uphill direction allowed by the constraints. The objective function and its gradients are again evaluated at the new point. If the value of the objective function has not been increased, the subroutine cuts back on its step size and reevaluates the objective function. This interpolation of the step size continues until the objective function is increased or a limit on the number of cutbacks allowed is reached.

The matrix of conjugate directions is then updated by using the newly found better value for the objective function and its gradient. All future steps are taken in the same direct manner as the first step except that instead of the true gradient, the conjugate gradient is used to determine the direction of the step. The conjugate gradient is derived from the true gradient by multiplying by the matrix of conjugate directions. For a more detailed explanation of the optimizer, reference is made to the Ph. D. thesis of Donald Goldfarb, entitled "A Conjugate Gradient Method for Nonlinear Programming," Ph. D. thesis, Princeton University, 1967. The optimization routine continues until it no longer improves the objective function, or the maximum number of passes through the optimization routine has been reached or the allowed time expires. Although a conjugate gradient optimizer has been described, other optimizer routines may be used with the objective function options of table I for optimization of a circuit design. For example, the optimizer routine of R. Fletcher and M. J. D. Powell, entitled "A Rapidly Convergent Descent Method for Minimization," British Computer Journal, Volume 6 (1963), pages 163 through 168 may be used. Another example of an acceptable optimizer routine mentioned in the Fletcher and Powell article is a direct search optimization routine commonly identified as the "Spider" routine. The latter routine is described in detail in a paper by R. Hooke and T. A. Jeever, entitled "Direct Search Solution of Numerical and Statistical Problems," Journal of the Association for Computing Machinery, Vol. 8, No. 2, pages 212-229, Apr. 1961.

After each pass through the optimizer routine of block 56, the objective function and its conjugate gradient are evaluated in terms of the Z-matrix of the select circuit topology in accordance with reselected options. The various evaluation options available are listed in table II with the equations used as follows (the various terms used in the following equations and the objective function options given in table I are listed in table II): ##SPC2##

Of particular significance to the improvement of a circuit design in accordance with the present invention is the various options available for generating the objective function. These objective function options result in the generation and storage of a value which depends on the sum of a power function of the difference between a specified performance characteristic and a calculated performance characteristic beyond a specified tolerance. Further, a circuit may be adjusted at a particular frequency such that the difference between a specified performance and a calculated performance is zero. In addition, where applicable, the calculated performance can be made to be greater than or less than a specified performance characteristic at a given frequency. Consider options 1 and 2 listed in table I. These two options are the same with the exception that for the second option GREF and NEQGRF (an index) are always zero. Let:

A(f.sub.k)=GN(f.sub.k)-GREF(f.sub.k)-GFLOAT

a1(f.sub.k)=ABS(A(f.sub.k))-GTOL

a2(f.sub.k)=0 if NEQGRF(f.sub.k)=1 and A(f.sub.k)>0

A2(f.sub.k)=0 if NEQGRF(f.sub.k)=-1 and A(f.sub.k)<0

A2(f.sub.k)=0 if A1(f.sub.k)<0

A2(f.sub.k)=A1(f.sub.k) otherwise;

then the contribution of option 1 or option 2 to the objective function is:

F=-.SIGMA..sub.f (A.sub.2 (f.sub.k)).sup.2.

Thus for the gain options 1 and 2, the calculated performance characteristic may be made to equal, be less than, or greater than the desired performance characteristic. Similarly, for option 7, a calculated attenuation versus frequency curve may be made to fit a specified curve to the degree required.

Referring again to that portion of the flow chart for the optimization of a selected circuit topology. Input data in the form of a selected circuit topology and objective function options are inputted to the memory 46 along with the number of passes (N) through the optimization routine and the frequency points (K) to be evaluated.

The optimization routine of Donald Goldfarb is as follows:

Let the current point be x.sup.i with a function value of f(x.sup.i) and a gradient g.sup.i =g(x.sup.i). It is assumed that x.sup.i is in R and lies in the (affine) subspace M.sub.q determined by the intersection of q linearly independent hyperplanes. The matrix operator H is therefore H.sub.q.sup.i. The conjugate-gradient algorithm is then:

1. Compute H.sub.q.sup.i g.sup.i,

and .alpha.=(N.sub.q 'N.sub.q).sup.-.sup.1 N.sub.q 'g.sup.i

If H.sub.q.sup.i g.sup.i =0 and .alpha. 0, then x.sup.i is global maximum.

2. If this is not the case, either H.sub.q.sup.i g.sup.i >max 0, 1/2.alpha..sub.q b.sub.qq.sup.-.sup.1/2 or H.sub.q.sup.i g.sup.i 1/2.alpha..sub.q b.sub.qq.sup.-.sup.1/2, where .alpha..sub.q b.sub.qq.sup.-.sup.1/2 .alpha..sub.i b.sub.ii.sup.-.sup.1/2, i=1, ..., q-1,

If the former holds proceed to step (3). If the latter applies, drop the q.sup.th hyperplane from the constraint basis and obtain H.sub.q.sub.-1.sup.i from

where P.sub.q.sub.-1 =I-N.sub.q.sub.-1 (N.sub.q.sub.-1 'N.sub.q.sub.-1).sup.-.sup.1 N.sub.q.sub.-1 '

Let q=q-1 and return to the beginning of step (2).

3. Let s.sup.i =H.sub.q.sup.i g.sup.i and compute .lambda. from the following formulas:

.lambda..sub.j =-(n.sub.j 'x.sup.i -b.sub.j)/n.sub.j 's.sup.i

(j=q+1, ..., k)

.lambda..sup.i =min .lambda..sub.j >o

Set x.sup.i.sup.+1 =x.sup.i +.lambda..sup.i s.sup.i and compute g.sup.i.sup.+1 =g(x.sup.i.sup.+1).

4. If s.sup.i, g.sup.i.sup.+1 0 and f(x.sup.i.sup.+1)>f(x.sup.i) set x.sup.i.sup.+1 =x.sup.i.sup.+1 and g.sup.i.sup.+1 =g.sup.i.sup.+1 and add to the constraint basis the hyperplane corresponding to the min .lambda..sub.j in step (3) above. H.sub.q.sub.+1.sup.i.sup.+1 is computed as follows:

Set q=q+1 and i=i+1 and return to step (1).

5. If s.sup.i 'g.sup.i.sup.+1 <0 obtain .gamma..sup.i,0<65.sup.i .lambda..sup.i, which maximizes f(x.sup.i +.gamma..sup.i s.sup.i). Set .sigma..sup.i =.gamma..sup.i s.sup.i and x.sup.i.sup.+1 =x.sup.i +.sigma..sup.i. Note that the intersection M.sub.q remains unchanged. Calculate g.sup.i.sup.+1 =g(x.sup.i.sup.+1) and set

y.sup.i =g.sup.i.sup.+1 -g.sup.i

Finally calculate value of H.sub.q.sup.i.sup.+1 from

H.sub.q.sup.i.sup.+1 =H.sub.q.sup.i +A.sup.i +B.sup.i

where

Set i=i+1 and return to step (1).

If the initial feasible point is an interior point of the allowable convex region R, H.sub.q.sup.o is initially chosen to be any positive definite symmetric matrix, usually I the identity matrix. However, if the initial point lies on the boundary B on exactly q linearly independent hyperplanes H.sub.q.sup.o is set equal to P.sub.q.

In the above algorithm, b.sub.i is the right-hand side of constraint; b.sub.ii is the i.sup.th diagonal element of (N.sub.q 'N.sub.q).sup.-.sup.1 ; f is the objective function; g is the vector gradient; n.sub.j is the unit normal to j.sup.th constraint; P is the number of constraints; q is the number of constraints in basis; s is the conjugate gradient direction s=H.sub.q g; y.sup.i is the difference in gradients between neighboring points y.sup.i =g.sup.i.sup.+1 -g.sup.i ; x is the solution variable vector; B is the boundary of feasible region; H.sub.q is the non-Euclidean projection operator basic to the conjugate gradient algorithm; I is the identity matrix; M.sub.q is the linear manifold formed by the intersection of q linearly independent hyperplanes; N.sub.q is the m.times.q basis matrix whose columns are the q linearly independent unit normals n.sub.i, i=1, ..., q; P.sub.q is the Euclidean projection operator which maps E.sup.m onto M.sub.q, where:

P.sub.q =I-N.sub.q (N.sub.q 'N.sub.q).sup.-.sup.1 N.sub.q ';

R is the feasible region; .alpha. is the vector of Lagrange multipliers (shadow prices) .alpha.=(N.sub.q 'N.sub.q).sup.-.sup.1 N.sub.q 'g; .gamma. is bound on the quadratic term in the equation where:

f(x)=f(x.sub.o)+(x-x.sub.o)'g(x.sub.o)+(x-x.sub.o)'(G(x')/2) (x-x.sub.o)

where g(x.sub.o) is the gradient of f(x) at x.sub.o ;

.gamma..sup.i is the scalar denoting distance in direction s.sup.i ; .lambda. is the distance in positive s direction to nearest constraint (defined in the equation where:

.lambda..sub.j =-(n.sub.j 'x.sup.i -b.sub.j)/n.sub.j 's.sup.i

(j=q+1, ..., k)

.lambda..sup.i =min .lambda..sub.j >0

Set x.sup.i.sup.+1 =x.sup.i +.lambda..sup.i s.sup.i and compute g.sup.i.sup.+1 =g(x.sup.i.sup.+1) ); k is the total number of inequality constraints; .sigma. is the distance along conjugate gradient direction to maximum in that direction .sigma..sup.i =.gamma..sup.i s.sup.i.

Assuming the use of a computer, such as the UNIVAC 1108, to optimize the selected circuit topology, a program listing of instructions to generate an objective function and its gradient for use in an optimization routine, such as that of Donald Goldfarb, is given in table III. The language of the program is FORTRAN 5. Instructions 36 through 40, 42 through 58, 65 through 70, 83 through 84, and 90 through 96 are scaling and timing instructions which are not required to generate an objective function and have not been included in table III. Other instructions which may not be self-explanatory are explained in table IV.

After the computer has carried out instructions 1 to 249, the objection function and its conjugate gradient are called by an optimizer program (block 56) that optimizes and adjusts the circuit topology design variables, as explained. If the circuit has not been optimized to the desired level or the programmed number of passes (N) has not been exceeded, the computer again utilizes instructions 1 through 249 of the program listing to generate a new objective function and conjugate gradient using the adjusted circuit element values. The new objective function and conjugate gradient are again called by the optimizer program to again optimize the circuit topology by adjusting circuit design variables. This sequence continues until the circuit is optimized to the desired level or the number of passes equals the programmed number (N). ##SPC3## ##SPC4## ##SPC5## ##SPC6##

After a given circuit topology has been optimized in a routine that generates and stores an admittance matrix and its derivatives and forms an objective function and its derivative, coded information representing the circuit topology and the final circuit element values are transferred to an analysis subroutine. In particular, the information is transferred to an analysis information section 58. The circuit is now analyzed at selected frequency points and in accordance with selected analysis options listed in table VII. For each selected frequency, the final optimized circuit and the circuit element values are analyzed (block 60) to determine the final circuit performance. After analysis at the last frequency point (k.sub.max) coded information representing the final circuit is transferred to either a calculator-computer plotter 62, a circuit layout routine 64, or readout and stored. At the completion of any of these last three options, a signal is transferred to the memory 46 to begin the optimization routine on another selected circuit topology.

TABLE VII. OPTIONS FOR ANALYSIS

Gain-- type determined by ncvp*--(db.)

Noise figure--(db.)

Mismatch at source--(db.)

Mismatch at load--(db.)

Input conductance--(mmhos)

Input susceptance (mmhos)

Output conductance (mmhos)

Output susceptance (mmhos)

Stability factor

phase--type determined by ncvp* (degrees)

Input vswr

output vswr

reflected phase angle (degrees)

Reflection loss

input resistance (ohms)

Input reactance (ohms)

Loaded stability factor

user supplied option

noise parameters

phase deviation

s11

s12

s21

s22

y11

y12

y21

y22

*ncvp = 1 for power gain, for phase of source voltage gain = 2 for current gain = 3 for voltage gain = 4 for source to load voltage gain

Referring to FIG. 4, the circuit illustrated is an example of a typical topology that may be optimized by the method of the present invention. The circuit includes shorted transmission lines 2a, 8a, 12a and 16a. In addition, the circuit includes series transmission lines 4a, 6a, 10a and 14a. Two transistors 17a and 18a complete a two-stage broad band amplifier. Assume that the elements and parameters have the starting values given in table VIII with the characteristic admittances (Y.sub.o) in millimhos and electrical lengths (.beta..sub.L) measured in fractions of a wavelength at 1.5 GHz. The source impedance is fixed at 20.000+J.000 millimhos and the load impedance fixed at 20.000+J.000 millimhos. Elements 17a and 18a are transistors with the following S parameters: ##SPC7##

This is fit to a fifth order polynomial in frequency

Referring to table I, options 1, 3 and 4 have been selected for the objective function, each having an equal weight distribution. This circuit was optimized at the following eight frequencies:

f= 0.90 GHz 1.00 1.20 1.40 1.60 1.80 2.00 2.10

After completion of twenty optimization passes through the routine (N=20), the optimized values of the circuit elements are given in table IX. Using the values of table IX and analyzed for a power gain (NCVP=1), the analysis results are given in table X. In addition to optimization and analysis results, a computer for optimization of the circuit of FIG. 4 also generated a readout giving the dimensions in inches for the transmission lines. These are listed in table XI and comprise the information used by the layout option 64, which may be a Gerber Plotter, to produce a pattern for fabricating the illustrated circuit. ##SPC8## ##SPC9## ##SPC10## ##SPC11##

In addition to optimizing a circuit of the type shown in FIG. 4, the method of the present invention may also be used for optimizing a circuit that has several switching states or modes, that is, elements that may be switched into and out of the circuit. Referring to FIG. 5, a circuit is shown having four switching modes or states. An input impedance 88 connects directly to one pole of a double-pole double-throw switch 90 and to the second pole through an inductor 92. Each branch of the circuit shown includes a resistor 94 in series with a capacitor 96. The first four branches are interconnected and connect directly to one pole of a double-pole double-throw switch 98 and to the second pole through an inductor 100. The second four branches are interconnected to an output impedance 104. Again, the circled numbers are the nodes for analysis and admittance matrix generation for the optimization routine.

Optimization of a multimode circuit of a type illustrated in FIG. 5 is similar to the optimization of a single-mode circuit. In addition to the previously described input information to the memory 46, a multimode circuit requires information identifying the number of modes. With reference to the program listing of table III, the data processor completes instructions 1 through 249 for mode one with the matrix generated from the circuit elements in the circuit in the first mode. This same routine is repeated for mode two using the circuit elements of the second mode to generate the admittance matrix and its derivative with respect to the design variables. For the circuit of FIG. 5, the routine set out in table III is repeated four times. Upon completion of the fourth mode, a composite value of the objective function and a composite value of its conjugate gradient are generated and stored for use by the optimizer routine of block 56.

In the optimizer routine, all the circuit elements in the various modes may be adjusted in a manner and a direction dependent upon the objective function and its conjugate gradient. If additional passes are to be made through the optimization routine, the program listing of table III is again used to evaluate the circuit in each of its four modes. In the logic flow chart of FIG. 3, the multimode instructions appear immediately below the optimizer routine block 56.

Comparing the optimization routine of a multimode circuit and a single mode circuit, the significant difference is in the generation of the objective function and its conjugate gradient. The same options as given in table I may be used for generating the objective function. In a single mode circuit, the subroutine given in table III is completed once for each optimization pass. For a multimode circuit, the subroutine of table III is repeated once for each mode for each optimization pass.

* * * * *

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