Bus master capable of relinquishing bus on request and retrying bus cycle
A bus master is provided with the capability to accept a data transfer task
from a CPU, which includes the performance of a predetermined sequence of
data transfer operations between memory and a selected peripheral
controlled by a respective controller. During any one of the operations,
the bus master may be requested to relinquish the bus so that a higher
priority transfer may occur or a deadlock condition resolved. In response
to such request, the bus master immediately terminates the current bus
cycle, but remembers the state thereof at the time of relinquishment.
After the high priority transfer is completed, the bus master may be
allowed to rearbitrate for use of the bus. Upon again obtaining control of
the bus, the bus master restarts the bus cycle which was prematurely
terminated and continues the sequence of operations as if no
relinquishment had occurred.
LaViolette; William P. (Austin, TX), Mothersole; David S. (Austin, TX), Zolnowsky; John (Austin, TX) |
July 28, 1983|