Non-volatile memory cell for programmable logic device
The present invention provides a memory cell which includes a pair of flash
EEPROM cells. One flash EEPROM cell is programmed and the other flash
EEPROM cell is simultaneously erased by a single programming pulse.
Because the configuration memory cell includes flash EEPROM cells, and
therefore is non-volatile, a power down does not require reprogramming or
refreshing of the configuration bit stored in the memory cell.
Rao; Kameswara K. (San Jose, CA) |
March 16, 1995|