Non-volatile memory device having SONOS structure and manufacturing method
A non-volatile memory device having a SONOS structure and a manufacturing
method thereof, where a conductive layer is formed between a charge trap
layer and a blocking insulation layer of the SONOS structure. Therefore,
when a voltage is applied to a gate, the conductive layer undergoes
voltage distributions. Accordingly, a desired voltage can be applied to
the blocking insulation layer, the charge trap layer and the tunnel
insulating layer by controlling the effective oxide thickness (EOT) of
the blocking insulation layer and the EOT of the charge trap layer and
the tunnel insulating layer. It is therefore possible to improve the
erase speed of a cell.
Om; Jae Chul (Seoul, KR) |
Hynix Semiconductor Inc.
March 8, 2007|