|United States Patent||8,156,351|
|Belmont , et al.||April 10, 2012|
An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.
|Inventors:||Belmont; Brian V. (West Linn, CA), Mishra; Animesh (Pleasanton, CA), Kardach; James P. (Saratoga, CA)|
|Filed:||December 2, 2008|
|Application Number||Filing Date||Patent Number||Issue Date|
|Current U.S. Class:||713/300 ; 713/320; 713/323|
|Current International Class:||G06F 1/00 (20060101); G06F 1/32 (20060101)|
|Field of Search:||713/300|
|5142684||August 1992||Perry et al.|
|6240521||May 2001||Barber et al.|
|6496919||December 2002||Nishimoto et al.|
|6631474||October 2003||Cai et al.|
|6725354||April 2004||Kahle et al.|
|7093147||August 2006||Farkas et al.|
|7100060||August 2006||Cai et al.|
Non-Final Office Action for U.S. Appl. No. 11/241,376, Mailed Apr. 7, 2008, 11 pages. cited by other .
Notice of Allowance for U.S. Appl. No. 11/241,376, Mailed Jul. 28, 2008, 4 pages. cited by other.