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United States Patent D810,036
Sawayanagi ,   et al. February 13, 2018

Semiconductor module


CLAIM The ornamental design for a semiconductor module, as shown and described.
Inventors: Sawayanagi; Satoshi (Matsumoto, JP), Taoka; Masahiro (Matsumoto, JP), Oose; Tomofumi (Matsumoto, JP), Takahashi; Hideaki (Omachi, JP)
Name City State Country Type




Assignee: FUJI ELECTRIC CO., LTD. (Kawasaki, JP)
Appl. No.: D/598,481
Filed: March 27, 2017

Foreign Application Priority Data

Nov 8, 2016 [JP] 2016-024300

Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;257/678,684,690,691 ;361/679.01,713,728,736,760,761,772,775,783,820 ;174/250,253 ;438/15,25,26,51,55,63,64

References Cited [Referenced By]

U.S. Patent Documents
4218724 August 1980 Kaufman
D317592 June 1991 Yoshizawa
5347160 September 1994 Sutrina
D357462 April 1995 Terasawa
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D357672 April 1995 Terasawa
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D772184 November 2016 Soyano
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D785577 May 2017 Kawase
D798832 October 2017 Hayashida
D799439 October 2017 Hayashiguchi
2001/0038143 November 2001 Sonobe
2003/0042584 March 2003 Yamaguchi
2010/0149774 June 2010 Matsumoto
2011/0044012 February 2011 Matsumoto
Primary Examiner: Oswecki; Elizabeth J


FIG. 1 is a front view of a semiconductor module showing our new design;

FIG. 2 is a rear view of the semiconductor module of FIG. 1;

FIG. 3 is a left side view of the semiconductor module of FIG. 1;

FIG. 4 is a right side view of the semiconductor module of FIG. 1;

FIG. 5 is a top view of the semiconductor module of FIG. 1;

FIG. 6 is a bottom view of the semiconductor module of FIG. 1; and,

FIG. 7 is a top, front, right side perspective view of the semiconductor module of FIG. 1.

The broken lines shown in the drawings represent portions of the semiconductor module that form no part of the claimed design.

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