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United States Patent D810,036
Sawayanagi ,   et al. February 13, 2018

Semiconductor module

Claims


CLAIM The ornamental design for a semiconductor module, as shown and described.
Inventors: Sawayanagi; Satoshi (Matsumoto, JP), Taoka; Masahiro (Matsumoto, JP), Oose; Tomofumi (Matsumoto, JP), Takahashi; Hideaki (Omachi, JP)
Applicant:
Name City State Country Type

FUJI ELECTRIC CO., LTD.

Kawasaki

N/A

JP
Assignee: FUJI ELECTRIC CO., LTD. (Kawasaki, JP)
Appl. No.: D/598,481
Filed: March 27, 2017

Foreign Application Priority Data

Nov 8, 2016 [JP] 2016-024300

Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;257/678,684,690,691 ;361/679.01,713,728,736,760,761,772,775,783,820 ;174/250,253 ;438/15,25,26,51,55,63,64

References Cited [Referenced By]

U.S. Patent Documents
4218724 August 1980 Kaufman
D317592 June 1991 Yoshizawa
5347160 September 1994 Sutrina
D357462 April 1995 Terasawa
D357671 April 1995 Terasawa
D357672 April 1995 Terasawa
5408128 April 1995 Furnival
5410450 April 1995 Iida
D360619 July 1995 Terasawa
D389808 January 1998 Yamada
D396450 July 1998 Nishiura
6078501 June 2000 Catrambone
D441726 May 2001 Sofue
6521983 February 2003 Yoshimatsu
6774465 August 2004 Lee
D606951 December 2009 Soyano
8107255 January 2012 Sakamoto
D686174 July 2013 Soyano
D705184 May 2014 Takahashi
D710319 August 2014 Chen
D712853 September 2014 Nakamura
D717253 November 2014 Jo
D717255 November 2014 Lim
D721048 January 2015 Nakamura
D721340 January 2015 Nakamura
D748595 February 2016 Bertalan
D754084 April 2016 Kawase
D762185 July 2016 Muehlensiep
D762597 August 2016 Bertalan
D766851 September 2016 Yoneyama
D767516 September 2016 Yoneyama
D772184 November 2016 Soyano
D773412 December 2016 Yoneyama
D773413 December 2016 Yoneyama
D774479 December 2016 Soyano
D785577 May 2017 Kawase
D798832 October 2017 Hayashida
D799439 October 2017 Hayashiguchi
2001/0038143 November 2001 Sonobe
2003/0042584 March 2003 Yamaguchi
2010/0149774 June 2010 Matsumoto
2011/0044012 February 2011 Matsumoto
Primary Examiner: Oswecki; Elizabeth J

Description



FIG. 1 is a front view of a semiconductor module showing our new design;

FIG. 2 is a rear view of the semiconductor module of FIG. 1;

FIG. 3 is a left side view of the semiconductor module of FIG. 1;

FIG. 4 is a right side view of the semiconductor module of FIG. 1;

FIG. 5 is a top view of the semiconductor module of FIG. 1;

FIG. 6 is a bottom view of the semiconductor module of FIG. 1; and,

FIG. 7 is a top, front, right side perspective view of the semiconductor module of FIG. 1.

The broken lines shown in the drawings represent portions of the semiconductor module that form no part of the claimed design.

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