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United States Patent D814,433
Soyano ,   et al. April 3, 2018

Semiconductor module

Claims


CLAIM The ornamental design for a semiconductor module, as shown and described.
Inventors: Soyano; Shin (Tokyo, JP), Takamiya; Yoshikazu (Tokyo, JP), Higuchi; Keiichi (Tokyo, JP), Koyama; Takahiro (Tokyo, JP)
Applicant:
Name City State Country Type

Fuji Electric Co., Ltd

Kawasaki-shi, Kanagawa

N/A

JP
Assignee: Fuji Electric Co., Ltd (Kawasaki-shi, JP)
Appl. No.: D/580,736
Filed: October 12, 2016

Related U.S. Patent Documents

Application NumberFiling DatePatent NumberIssue Date
29528214May 27, 2015D774479

Foreign Application Priority Data

Nov 28, 2014 [JP] D2014-026634
Nov 28, 2014 [JP] D2014-026635
Nov 28, 2014 [JP] D2014-026636

Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;257/678,684,690,691 ;361/679.01,713,728,736,760,761,772,775,783,820 ;174/250,253 ;438/15,25,26,51,55,63,64,106

References Cited [Referenced By]

U.S. Patent Documents
5347160 September 1994 Sutrina
D357671 April 1995 Terasawa
D357672 April 1995 Terasawa et al.
D360619 July 1995 Terasawa
D389808 January 1998 Yamada
D396450 July 1998 Nishiura et al.
D441726 May 2001 Sofue et al.
6521983 February 2003 Yoshimatsu et al.
D476959 July 2003 Yamada
D587662 March 2009 Soutome et al.
D589012 March 2009 Soyano et al.
D606951 December 2009 Soyano et al.
D653633 February 2012 Soyano
D653634 February 2012 Soyano
D686174 July 2013 Soyano
D689446 September 2013 Soyano
D704670 May 2014 Chen et al.
D704671 May 2014 Chen et al.
D705184 May 2014 Takahashi et al.
D706232 June 2014 Nakamura
D710317 August 2014 Chen et al.
D710318 August 2014 Chen et al.
D710319 August 2014 Chen et al.
D712853 September 2014 Nakamura
D721048 January 2015 Nakamura
D721340 January 2015 Nakamura
D724554 March 2015 Motohashi et al.
D748595 February 2016 Bertalan et al.
D754084 April 2016 Kawase
D759604 June 2016 Yoneyama
D762185 July 2016 Muehlensiep
D762597 August 2016 Bertalan
D766851 September 2016 Yoneyama
D767516 September 2016 Yoneyama
D772184 November 2016 Soyano
D773412 December 2016 Yoneyama
D773413 December 2016 Yoneyama
D774479 December 2016 Soyano
D775091 December 2016 Edenharter
D775593 January 2017 Edenharter
D776071 January 2017 Edenharter
D785577 May 2017 Kawase
2001/0038143 November 2001 Sonobe et al.
2010/0149774 June 2010 Matsumoto et al.
2011/0044012 February 2011 Matsumoto

Other References

US. Appl. No. 29/580,738, filed Oct. 12, 2016. cited by applicant.

Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Young Basile Hanlon & MacFarlane, P.C.

Description



FIG. 1 is a front view of a semiconductor module showing our new design.

FIG. 2 is a rear view of the semiconductor module of FIG. 1.

FIG. 3 is a left side view of the semiconductor module of FIG. 1.

FIG. 4 is a right side view of the semiconductor module of FIG. 1.

FIG. 5 is a top view of the semiconductor module of FIG. 1.

FIG. 6 is a bottom view of the semiconductor module of FIG. 1.

FIG. 7 is a front, right, and bottom perspective view of the semiconductor module of FIG. 1; and,

FIG. 8 is a rear, left, and top perspective view of the semiconductor module of FIG. 1.

The ornamental design of the present disclosure is a semiconductor module on which power semiconductor elements and the like may be mounted. Terminals extend from a circumferential edge part of a front surface. Rhombic plate members having rounded corners are centered along the long sides of the rear view, such that the longer diagonal line of each rhombic plate member extends along a long side.

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