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United States Patent D827,591
Ikeda ,   et al. September 4, 2018

Semiconductor module


CLAIM The ornamental design for a semiconductor module, as shown and described.
Inventors: Ikeda; Yoshinari (Matsumoto, JP), Hori; Motohito (Matsumoto, JP), Hinata; Yuichiro (Matsumoto, JP), Daicho; Norihiro (Matsumoto, JP)
Name City State Country Type




Assignee: FUJI ELECTRIC CO., LTD. (Kawasaki, JP)
Appl. No.: D/601,253
Filed: April 20, 2017

Foreign Application Priority Data

Oct 31, 2016 [JP] 2016-023736

Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;257/678,684,690,691 ;361/679.01,713,728,736,760,761,772,775,783,820 ;174/250,253 ;438/15,25,26,51,55,63,64,106

References Cited [Referenced By]

U.S. Patent Documents
5347160 September 1994 Sutrina
D357672 April 1995 Terasawa
D364383 November 1995 Yamada
D364384 November 1995 Shimizu
D364385 November 1995 Shimizu
5512782 April 1996 Kobayashi
D389808 January 1998 Yamada
D476959 July 2003 Yamada
6774465 August 2004 Lee
D587662 March 2009 Soutome
D648290 November 2011 Mori
D703625 April 2014 Lim
D704670 May 2014 Chen
D710317 August 2014 Chen
D710318 August 2014 Chen
D710319 August 2014 Chen
D712853 September 2014 Nakamura
D721048 January 2015 Nakamura
D721340 January 2015 Nakamura
D748595 February 2016 Bertalan
D754084 April 2016 Kawase
D762185 July 2016 Muehlensiep
D762597 August 2016 Bertalan
D766851 September 2016 Yoneyama
D767516 September 2016 Yoneyama
D772184 November 2016 Soyano
D773412 December 2016 Yoneyama
D773413 December 2016 Yoneyama
D774479 December 2016 Soyano
D785577 May 2017 Kawase
D798832 October 2017 Hayashida
D799439 October 2017 Hayashiguchi
D805485 December 2017 Kawase
D810036 February 2018 Sawayanagi
D810706 February 2018 Soyano
D814431 April 2018 Matsumoto
D814433 April 2018 Soyano
Primary Examiner: Oswecki; Elizabeth J


FIG. 1 is a front view of a semiconductor module showing our new design;

FIG. 2 is a rear view of the semiconductor module of FIG. 1;

FIG. 3 is a left side view of the semiconductor module of FIG. 1;

FIG. 4 is a right side view of the semiconductor module of FIG. 1;

FIG. 5 is a top view of the semiconductor module of FIG. 1;

FIG. 6 is a bottom view of the semiconductor module of FIG. 1;

FIG. 7 is a top, front, and right side perspective view of the semiconductor module of FIG. 1; and,

FIG. 8 is a cross sectional view taken along line 8-8 of FIG. 5.

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