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United States Patent Application 20170206849
Kind Code A1
WU; Jingjing ;   et al. July 20, 2017

Source Driving Module and Liquid Crystal Display Panel

Abstract

A source driving module includes: n data input channels, receiving n data signals from the timing controller; n level shifters, coupled to the n data input channels; n digital to analog converters, coupled to the n level shifters; N switches, divided into N n ##EQU00001## switch groups, each switch group coupled to the n digital to analog converters; N buffers, divided into N n ##EQU00002## buffer groups, each buffer group coupled to one of the N n ##EQU00003## switch groups; a frequency divider, for converting clock signal into switch controlling signal to alternatively switch on the N n ##EQU00004## switch groups. During a mth period of data transmission, the n data input channels receive data signals of n pixels from the timing controller, and the data signals of n pixels is fed to a mth buffer group via a mth switch group upon receiving the switch controlling signal. The present invention also proposes an LCD panel using the source driving module.


Inventors: WU; Jingjing; (Shenzhen, Guangdong, CN) ; XIONG; Zhi; (Shenzhen, Guangdong, CN)
Applicant:
Name City State Country Type

Shenzhen China Star Optoelectronics Technology Co., Ltd.

Shenzhen, Guangdong

CN
Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
Shenzhen, Guangdong
CN

Family ID: 1000002541756
Appl. No.: 14/770140
Filed: July 17, 2015
PCT Filed: July 17, 2015
PCT NO: PCT/CN2015/084377
371 Date: February 6, 2017


Current U.S. Class: 1/1
Current CPC Class: G09G 3/3688 20130101; G09G 3/3648 20130101; G09G 2310/08 20130101; G09G 2310/027 20130101; G09G 2310/0289 20130101
International Class: G09G 3/36 20060101 G09G003/36

Foreign Application Data

DateCodeApplication Number
Jul 6, 2015CN201510392243.9

Claims



1. A source driving module for supplying data signals sent from a timing controller to a plurality of subpixels of a liquid crystal display panel, N subpixels being arranged in a row, the source driving module comprising: n data input channels, receiving n data signals from the timing controller; n level shifters, coupled to the n data input channels; n digital to analog converters, coupled to the n level shifters; N switches, divided into N n ##EQU00025## switch groups, each switch group coupled to the n digital to analog converters; N buffers, divided into N n ##EQU00026## buffer groups, each buffer group coupled to one of the N n ##EQU00027## switch groups; a frequency divider, for converting a clock signal sent from the timing controller into a switch controlling signal to alternatively switch on the N n ##EQU00028## switch groups; wherein during a mth period of data transmission, the n data input channels receive data signals of n pixels from the timing controller, and the data signals of n pixels is fed to a mth buffer group via a mth switch group upon receiving the switch controlling signal, where N is an integer greater than 1, n is an even number, N>>n, N n ##EQU00029## is an integer greater than 1, and m=1, 2, 3, . . . , N n ; ##EQU00030## when receiving the data signals, the N buffers are controlled to transmit the data signals to the N subpixels by the timing controller.

2. The source driving module of claim 1, wherein 2.ltoreq.n.ltoreq.10.

3. The source driving module of claim 1, wherein n=6.

4. The source driving module of claim 1, wherein a period of data transmission and is several times of a duty cycle of the clock signal, and a duty cycle of the switching controlling signal equals to the period of data transmission, the period of data transmission indicates a period which each data input channel receive data signal of a pixel from the timing controller.

5. The source driving module of claim 4, wherein each data input channel receive a 8-bit digital data signal during the period of data transmission.

6. The source driving module of claim 5, wherein the period of data transmission comprises four duty cycles of the clock signal.

7. A liquid crystal display (LCD) panel comprising: a display unit, comprising a plurality of subpixels, N subpixels being arranged in a row; a timing controller; a gate driving module, controlled by the timing controller to supply scan signal to the plurality of subpixels; and a source driving module, controlled by the timing controller to supply data signal to the plurality of subpixels, comprising: n data input channels, receiving n data signals from the timing controller; n level shifters, coupled to the n data input channels; n digital to analog converters, coupled to the n level shifters; N switches, divided into N n ##EQU00031## switch groups, each switch group coupled to the n digital to analog converters; N buffers, divided into N n ##EQU00032## buffer groups, each buffer group coupled to one of the N n ##EQU00033## switch groups; a frequency divider, for converting a clock signal sent from the timing controller into a switch controlling signal to alternatively switch on the N n ##EQU00034## switch groups; wherein during a mth period of data transmission, the n data input channels receive data signals of n pixels from the timing controller, and the data signals of n pixels is fed to a mth buffer group via a mth switch group upon receiving the switch controlling signal, where N is an integer greater than 1, n is an even number, N>>n, N n ##EQU00035## is an integer greater than 1, and m=1, 2, 3, . . . , N n ; ##EQU00036## when receiving the data signals, the N buffers are controlled to transmit the data signals to the N subpixels by the timing controller.

8. The LCD panel of claim 7, wherein 2.ltoreq.n.ltoreq.10.

9. The LCD panel of claim 7, wherein n=6.

10. The LCD panel of claim 7, wherein a period of data transmission and is several times of a duty cycle of the clock signal, and a duty cycle of the switching controlling signal equals to the period of data transmission, the period of data transmission indicates a period which each data input channel receive data signal of a pixel from the timing controller.

11. The LCD panel of claim 10, wherein each data input channel receive a 8-bit digital data signal during the period of data transmission.

12. The LCD panel of claim 11, wherein the period of data transmission comprises four duty cycles of the clock signal.
Description



BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of liquid crystal display technology, and more particularly, to a source driving module and a liquid crystal display (LCD) panel having the source driving module.

[0003] 2. Description of the Prior Art

[0004] A liquid crystal display (LCD) has such merits of thinness, lightness, power saving, and low radiation as to be applied in notebook computers, mobile phones, electronic dictionaries and other electronic display devices. As per the LCD technology having been developing, so changes the environment in which the electronic display devices are used. They are more often used outdoors. Demand on visual effects is rising, so a LCD device of greater lightness is expected. The LCD panel is a main component of the LCD. The LCD panel includes a color filter substrate, a thin film transistor (TFT) array substrate and a liquid crystal layer therebetween.

[0005] The LCD panel is driven by a gate driving module and a source driving module for supplying scan signals and data signals to pixels. Various voltage drops between the data signal and a common voltage induces liquid crystals rotating in different angles to show different brightness, so that the LCD panel shows various grey levels. As shown in FIG. 1, a conventional source driving module includes bi-directional shift registers S/R, latches L, level shifters L/S, digital to analog converters DAC, and buffers B. Digital signals from a timing controller (TCOM) are fed to the latches L via bi-directional shift registers S/R. The level shifters L/S boost voltages of the digital signals, and then the digital to analog converters DAC convert the digital signal into analog signals and transmit to the buffers B. The buffers B output the analog signals to the pixels. As shown in FIG. 1, when there are N pixels arranged in a row, the source driving module supplies N signals to the N pixels. Therefore, the source driving module requires N bi-directional shift registers S/R.sub.1.about.S/R.sub.N, N latches L.sub.1.about.L.sub.N, N level shifters L/S.sub.1.about.L/N.sub.N, N digital to analog converters DAC.sub.l.about.DAC.sub.N, and N buffers B.sub.1.about.B.sub.N. Each data input channel has a bi-directional shift register S/R, a latch L, a level shifter L/S, a digital to analog converter DAC, and a buffer B. In other words, there are many pixels in a row, i.e. N is a great integer. The conventional source driving module includes more elements and high cost.

SUMMARY OF THE INVENTION

[0006] In view of the deficiency of the conventional technology, the present invention provides a source driving module of which each sub-module comprises less elements, thereby reducing costs.

[0007] According to the present invention, a source driving module for supplying data signals sent from a timing controller to a plurality of subpixels of a liquid crystal display panel is provided. N subpixels are arranged in a row. The source driving module comprises: n data input channels, receiving n data signals from the timing controller; n level shifters, coupled to the n data input channels; n digital to analog converters, coupled to the n level shifters; N switches, divided into

N n ##EQU00005##

switch groups, each switch group coupled to the n digital to analog converters; N buffers, divided into

N n ##EQU00006##

buffer groups, each buffer group coupled to one of the

N n ##EQU00007##

switch groups; a frequency divider, for converting a clock signal sent from the timing controller into a switch controlling signal to alternatively switch on the

N n ##EQU00008##

switch groups. During a mth period of data transmission, the n data, input channels receive data signals of n pixels from the timing controller, and the data signals of n pixels is fed to a mth buffer group via a mth switch group upon receiving the switch controlling signal, where N is an integer greater than 1, n is an even number, N>>n,

N n ##EQU00009##

is an integer greater than 1, and m=1, 2, 3, . . . ,

N n . ##EQU00010##

When receiving the data signals, the N buffers are controlled to transmit the data signals to the N subpixels by the timing controller.

[0008] In one aspect of the present invention, 2.ltoreq.n.ltoreq.10.

[0009] In another aspect of the present invention, n=6.

[0010] In another aspect of the present invention, a period of data transmission and is several times of a duty cycle of the clock signal, and a duty cycle of the switching controlling signal equals to the period of data transmission, the period of data transmission indicates a period which each data input channel receive data signal of a pixel from the timing controller.

[0011] In still another aspect of the present invention, each data input channel receive a 8-bit digital data signal during the period of data transmission.

[0012] In yet another aspect of the present invention, the period of data transmission comprises four duty cycles of the clock signal.

[0013] According to the present invention, a liquid crystal display (LCD) panel comprises a display unit comprising a plurality of subpixels, a timing controller, a gate driving module controlled by the timing controller to supply scan signal to the plurality of subpixels, and a source driving module controlled by the timing controller to supply data signal to the plurality of subpixels. The source driving module comprises elements as suggested above.

[0014] In contrast to prior art, the present invention provides a source driving module of which each sub-module comprises less elements, thereby reducing costs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 is a schematic diagram of a conventional source driving module.

[0016] FIG. 2 is a block diagram of a source driving module according to a preferred embodiment of the present invention.

[0017] FIG. 3 is a schematic diagram of a source driving module according to a preferred embodiment of the present invention.

[0018] FIG. 4 is a timing diagram of a switch controlling signal and a clock signal according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.

[0020] Referring to FIG. 2, a liquid crystal display (LCD) panel 100 comprises a display unit 10, a timing controller 20, a source driving module 30, and a gate driving module 40. The display unit 10 comprises a plurality of subpixels P. There are N subpixels P.sub.1, P.sub.2, . . . , P.sub.N in a row. The timing controller 20 controls the source driving module 30 to supply data signal to the subpixel P and controls the gate driving module 40 to supply scan signal to the subpixel P.

[0021] Referring to FIG. 3, according to the preferred embodiment of the present invention, the source driving module 30 comprises n data input channels, n level shifters, n digital to analog converters (DACs), N switches (divided into

N n ##EQU00011##

groups), N buffers (divided into

N n ##EQU00012##

groups), and a frequency divider, where N is an integer greater than 1, n is an even number, N>>n, and

N n ##EQU00013##

is an integer greater than 1. N depends on the number of subpixels in a row of the display unit 10, e.g. 960 or 1024. Because N is much greater than n, n is preferred selected from 2.ltoreq.n.ltoreq.10.

[0022] In this embodiment, n=6 is selected as an example.

[0023] As shown in FIG. 3, the source driving module 30 comprises six data input channels C.sub.1.about.C.sub.6, six level shifters L/S.sub.1.about.L/S.sub.6, six digital to analog converters DAC.sub.1.about.DAC.sub.6, N switches SW.sub.1.about.SW.sub.N, N buffers B.sup.1.about.B.sub.N, and a frequency divider 31.

[0024] The six data input channels C.sub.1.about.C.sub.6 receive six data signals Data from the timing controller 20. The data signals Data is digital signal.

[0025] The six level shifters L/S.sub.1.about.L/S.sub.6 are respectively connected to the six data input channels and are used for boosting voltages of the digital data signals Data.

[0026] The six digital to analog converters DAC.sub.1.about.DAC.sub.6 are respectively connected to the six level shifters L/S.sub.1.about.L/S.sub.6, and are used for converting the digital data signals Data into analog signal.

[0027] N switches SW.sub.1.about.SW.sub.N are divided into

N 6 ##EQU00014##

switch groups, each group comprises six switches respectively connected to the six digital to analog converters DAC.sub.1.about.DAC.sub.6. Specifically, the first switch group has six switches SW.sub.1.about.SW.sub.6 respectively connected to the six digital to analog converters DAC.sub.1.about.DAC.sub.6. The second switch group has six switches SW.sub.7.about.SW.sub.12 respectively connected to the six digital to analog converters DAC.sub.1.about.DAC.sub.6. Similarly the

( N 6 ) th ##EQU00015##

switch group has six switches SW.sub.N-5.about.SW.sub.N respectively connected to the six digital to analog converters DAC.sub.1.about.DAC.sub.6.

[0028] The N buffers B.sup.1.about.B.sub.N respectively connected to the N switches SW.sub.1.about.SW.sub.N. In another aspect, the N buffers B.sup.1.about.B.sub.N are divided into

N 6 ##EQU00016##

buffer groups. Specifically, the first buffer group has six buffers B.sub.1.about.B.sub.6 respectively connected to the six switches SW.sub.1.about.SW.sub.6. The second buffer group has six buffers B.sub.7.about.B.sub.12 respectively connected to the six switches SW.sub.7.about.SW.sub.12. Similarly the

( N 6 ) th ##EQU00017##

buffer group has six buffer B.sub.N-5.about.B.sub.N respectively connected to the six switches SW.sub.N-5.about.SW.sub.N.

[0029] The frequency divider 31 converts a clock signal CLK sent from the timing controller 20 into a switch controlling signal SC, for alternatively switching on the

N 6 ##EQU00018##

switch groups. A duty cycle of the switching controlling signal SC equals to a period of data transmission and is several times of a duty cycle of the clock signal CLK. The period of data transmission indicates a period which all the six data input channels C.sub.1.about.C.sub.6 receive digital data signal of a pixel from the timing controller 20. For instance, the timing controller 20 outputs a 8-bit digital data signal of a pixel. Since the six data input channels C.sub.1.about.C.sub.6 receive the 8-bit digital data signal in four duty cycles of the clock signal CLK, the period of data transmission is four duty cycles of the clock signal CLK. Accordingly, the duty cycle of the switch controlling signal also equals to four duty cycles of the clock signal CLK, as shown in FIG. 4.

[0030] Processes relating to the source driving module 30 transmitting the data signal are introduced as follows: during the mth period of data transmission, the six data input channels C.sub.1.about.C.sub.6 receive data signals of six pixels from the timing controller 20, switches of the mth switch group are all turned on upon receiving the switch controlling signal SC, while switches of the other switch groups are turned off, where m=1, 2, 3, . . . ,

N n . ##EQU00019##

The data signals of the six pixels are transmitted to the mth buffer group through the turned on switches of the mth switch group. After the N buffers B.sub.1.about.B.sub.N receive the data signals, i.e. the data signals of subpixels P.sub.1.about.P.sub.N in a row, the timing controller 20 transmits holding signal TP to the buffers B.sub.1.about.B.sub.N, so as to control the buffers B.sup.1.about.B.sub.N conducting the digital signals to the subpixels P.sub.1.about.P.sub.N.

[0031] Specifically, during a first period of data transmission, the switches SW.sub.1.about.SW.sub.6 turn on while the other switches turn off in the first cycle of the switch controlling signal SC. At this moment, six data signals which are sent from the timing controller 20 and received by the data input channels C.sub.1.about.C.sub.6 are fed to the buffers B.sub.1.about.B.sub.6 through the switches SW.sub.1.about.SW.sub.6. During a second period of data transmission, the switches SW.sub.7.about.SW.sub.12 turn on while the other switches turn off in the second cycle of the switch controlling signal SC. At this moment, six data signals which are sent from the timing controller 20 and received by the data input channels C.sub.1.about.C.sub.6 are fed to the buffers B.sub.7.about.B.sub.12 through the switches SW.sub.7.about.SW.sub.12. Similarly, during a

( N 6 ) th ##EQU00020##

period of data transmission, the switches SW.sub.N-5.about.SW.sub.N of the

( N 6 ) th ##EQU00021##

switch group turn on while the other switches turn off in the

( N 6 ) th ##EQU00022##

cycle of the switch controlling signal SC. At this moment, six data signals which are sent from the timing controller 20 and received by the data input channels C.sub.1.about.C.sub.6 are fed to the buffers B.sub.N-5.about.B.sub.N of the

( N 6 ) th ##EQU00023##

buffer group through the switches SW.sub.N-5.about.SW.sub.N of the

( N 6 ) th ##EQU00024##

switch group. After the N buffers B.sub.1.about.B.sub.N receive the data signals, i.e. the data signals of subpixels P.sub.1.about.P.sub.N in a row, the timing controller 20 controls the buffers B.sub.1.about.B.sub.N conducting the digital signals to the subpixels P.sub.1.about.P.sub.N.

[0032] In the source driving module according to the present invention, each sub-module comprises less elements, thereby reducing costs. Take 960 subpixles in each row (i.e. N=960) as an example, the conventional source driving module, as shown in FIG. 1, includes 960 bi-directional shift registers S/R.sub.1.about.S/R.sub.N, 960 latches L.sub.1.about.L.sub.N, 960 level shifters L/S.sub.1.about.L/S.sub.N, 960 digital to analog converters DAC.sub.1.about.DAC.sub.N, and 960 buffers B.sub.1.about.B.sub.N. Rather, the present inventive source driving module, as shown in FIG. 2, comprises 6 level shifters L/S.sub.1.about.L/S.sub.6, 6 digital to analog converters DAC.sub.1.about.DAC.sub.6, 960 switches SW.sub.1.about.SW.sub.960, 960 buffers B.sub.1.about.B.sub.960, and a frequency divider 31. By contrast, the present inventive source driving module not only omits bi-directional shift registers and latches, but also reduces the number of level shifters and digital to analog converters. Although the present inventive source driving module adds more switches and a frequency divider, the number of required elements applied in each sub-module decrease. Therefore, the layout of the present inventive source driving module is simplified and reduces cost.

[0033] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

* * * * *

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